ARM:tegra:emc: scale latency allowance by tick len

Calculate the tick length of the EMC DFS table
and scale the latency allowance settings.

Bug 955082

Change-Id: Id7b1504c6854009ba7677c7ddebe0a8f62cbfb7e
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/124980
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

1 files changed, 44 insertions, 1 deletions

diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c
index 57a673b4df8d..4c06bf91ab1f 100644
--- a/arch/arm/mach-tegra/tegra3_emc.c
+++ b/arch/arm/mach-tegra/tegra3_emc.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra3_emc.c
  *
- * Copyright (C) 2012 NVIDIA Corporation
+ * Copyright (C) 2011-2012, NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -33,6 +33,7 @@
 #include <asm/cacheflush.h>
 
 #include <mach/iomap.h>
+#include <mach/latency_allowance.h>
 
 #include "clock.h"
 #include "dvfs.h"
@@ -1018,6 +1019,31 @@ static struct notifier_block tegra_emc_resume_nb = {
 	.priority = -1,
 };
 
+static int tegra_emc_get_table_ns_per_tick(unsigned int emc_rate,
+					unsigned int table_tick_len)
+{
+	unsigned int ns_per_tick = 0;
+	unsigned int mc_period_10ns = 0;
+	unsigned int reg;
+
+	reg = mc_readl(MC_EMEM_ARB_MISC0) & MC_EMEM_ARB_MISC0_EMC_SAME_FREQ;
+
+	mc_period_10ns = ((reg ? (NSEC_PER_MSEC * 10) : (20 * NSEC_PER_MSEC)) /
+			(emc_rate));
+	ns_per_tick = ((table_tick_len & MC_EMEM_ARB_CFG_CYCLE_MASK)
+		* mc_period_10ns) / (10 *
+		(1 + ((table_tick_len & MC_EMEM_ARB_CFG_EXTRA_TICK_MASK)
+		>> MC_EMEM_ARB_CFG_EXTRA_TICK_SHIFT)));
+
+	/* round new_ns_per_tick to 30/60 */
+	if (ns_per_tick < 45)
+		ns_per_tick = 30;
+	else
+		ns_per_tick = 60;
+
+	return ns_per_tick;
+}
+
 void tegra_init_emc(const struct tegra_emc_table *table, int table_size)
 {
 	int i, mv;
@@ -1025,6 +1051,8 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size)
 	bool max_entry = false;
 	unsigned long boot_rate, max_rate;
 	struct clk *cbus = tegra_get_clock_by_name("cbus");
+	unsigned int ns_per_tick = 0;
+	unsigned int cur_ns_per_tick = 0;
 
 	emc_stats.clkchange_count = 0;
 	spin_lock_init(&emc_stats.spinlock);
@@ -1085,6 +1113,19 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size)
 
 		if (table_rate == max_rate)
 			max_entry = true;
+
+		cur_ns_per_tick = tegra_emc_get_table_ns_per_tick(table_rate,
+				table[i].burst_regs[MC_EMEM_ARB_CFG_INDEX]);
+
+		if (ns_per_tick == 0) {
+			ns_per_tick = cur_ns_per_tick;
+		} else if (ns_per_tick != cur_ns_per_tick) {
+			pr_err("tegra: invalid EMC DFS table: "
+				"mismatched DFS tick lengths "
+				"within table!\n");
+			ns_per_tick = 0;
+			return;
+		}
 	}
 
 	/* Validate EMC rate and voltage limits */
@@ -1094,6 +1135,8 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size)
 		return;
 	}
 
+	tegra_latency_allowance_update_tick_length(ns_per_tick);
+
 	tegra_emc_table = table;
 
 	adjust_emc_dvfs_table(tegra_emc_table, tegra_emc_table_size);