diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-11-01 19:39:15 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:49:56 -0800 |
| commit | 529ed3a4eef9a419faefc700565cd442c102e778 (patch) | |
| tree | b4011a06d124db859f1f4043b1ce13036520ca63 /arch/arm/mach-tegra/tegra3_emc.c | |
| parent | 360c820c784b113f0f85ea3e632e9e6ecf2a94a8 (diff) | |
ARM: tegra: clock: Add DSR field to Tegra3 EMC DFS table
Added dynamic self-refresh (DSR) field to Tegra3 EMC DFS table. This
field will be supported starting with table revision to 3.2, and it
will allow to enable/disable DSR for each table entry independently.
Bug 853990
(cherry picked from commit 6e225af7334d789ffac72542602913a0028d5eac)
(cherry picked from commit c7ebe73da695206a992088a4ba5a6cd7643ea333)
Change-Id: I212d5992067baffaaf5b2e1de25b103c7b1fb56a
Reviewed-on: http://git-master/r/63356
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R7261d49b023634a783ab2bd55f494112d0bac2a1
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_emc.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_emc.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c index 49833f28f56a..56d579972369 100644 --- a/arch/arm/mach-tegra/tegra3_emc.c +++ b/arch/arm/mach-tegra/tegra3_emc.c @@ -567,6 +567,8 @@ static noinline void emc_set_clock(const struct tegra_emc_table *next_timing, EMC_AUTO_CAL_INTERVAL); /* 16. restore dynamic self-refresh */ + if (next_timing->rev >= 0x32) + dyn_sref_enabled = next_timing->emc_dsr; if (dyn_sref_enabled) { emc_cfg_reg |= EMC_CFG_DYN_SREF_ENABLE; emc_writel(emc_cfg_reg, EMC_CFG); @@ -606,9 +608,13 @@ static inline void emc_get_timing(struct tegra_emc_table *timing) static inline void emc_cfg_power_restore(void) { u32 reg = emc_readl(EMC_CFG); - if ((reg ^ emc_cfg_saved) & EMC_CFG_PWR_MASK) { - reg = (reg & (~EMC_CFG_PWR_MASK)) | - (emc_cfg_saved & EMC_CFG_PWR_MASK); + u32 pwr_mask = EMC_CFG_PWR_MASK; + + if (tegra_emc_table[0].rev >= 0x32) + pwr_mask &= ~EMC_CFG_DYN_SREF_ENABLE; + + if ((reg ^ emc_cfg_saved) & pwr_mask) { + reg = (reg & (~pwr_mask)) | (emc_cfg_saved & pwr_mask); emc_writel(reg, EMC_CFG); emc_timing_update(); } @@ -845,6 +851,7 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) emc_num_burst_regs = 105; break; case 0x31: + case 0x32: emc_num_burst_regs = 107; break; default: |