diff options
| author | Ray Poudrier <rapoudrier@nvidia.com> | 2012-08-21 12:23:51 -0700 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-08-24 18:11:40 -0700 |
| commit | 2b7b55a2a52fc714d0074598bb81bae277e6b1e9 (patch) | |
| tree | 2af1d6f288bc154c130648361edcb67ae2663f64 /arch/arm/mach-tegra/tegra3_emc.h | |
| parent | 247c373c149d6997814eb2b7b2336b78efcab1a8 (diff) | |
ARM:tegra:emc: scale latency allowance by tick len
Calculate the tick length of the EMC DFS table
and scale the latency allowance settings.
Bug 955082
Change-Id: Id7b1504c6854009ba7677c7ddebe0a8f62cbfb7e
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/124980
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_emc.h')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_emc.h | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra3_emc.h b/arch/arm/mach-tegra/tegra3_emc.h index 29b4556d749d..43ef636c613f 100644 --- a/arch/arm/mach-tegra/tegra3_emc.h +++ b/arch/arm/mach-tegra/tegra3_emc.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/tegra3_emc.h * - * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -267,6 +267,10 @@ enum { #define MC_EMEM_ADR_CFG 0x54 #define MC_EMEM_ARB_CFG 0x90 +#define MC_EMEM_ARB_CFG_CYCLE_MASK 0x1ff +#define MC_EMEM_ARB_CFG_EXTRA_TICK_SHIFT 16 +#define MC_EMEM_ARB_CFG_EXTRA_TICK_MASK \ + (0x1f << MC_EMEM_ARB_CFG_EXTRA_TICK_SHIFT) #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_SHIFT 0 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK \ @@ -295,6 +299,43 @@ enum { #define MC_EMEM_ARB_OVERRIDE 0xe8 #define MC_EMEM_ARB_OVERRIDE_EACK_MASK (0x3 << 0) #define MC_TIMING_CONTROL 0xfc +#define MC_LATENCY_ALLOWANCE_AFI 0x2e0 +#define MC_LATENCY_ALLOWANCE_AVPC 0x2e4 +#define MC_LATENCY_ALLOWANCE_DC_0 0x2e8 +#define MC_LATENCY_ALLOWANCE_DC_1 0x2ec +#define MC_LATENCY_ALLOWANCE_DC_2 0x2f0 +#define MC_LATENCY_ALLOWANCE_DCB_0 0x2f4 +#define MC_LATENCY_ALLOWANCE_DCB_1 0x2f8 +#define MC_LATENCY_ALLOWANCE_DCB_2 0x2fc +#define MC_LATENCY_ALLOWANCE_EPP_0 0x300 +#define MC_LATENCY_ALLOWANCE_EPP_1 0x304 +#define MC_LATENCY_ALLOWANCE_G2_0 0x308 +#define MC_LATENCY_ALLOWANCE_G2_1 0x30c +#define MC_LATENCY_ALLOWANCE_HC_0 0x310 +#define MC_LATENCY_ALLOWANCE_HC_1 0x314 +#define MC_LATENCY_ALLOWANCE_HDA 0x318 +#define MC_LATENCY_ALLOWANCE_ISP 0x31c +#define MC_LATENCY_ALLOWANCE_MPCORE 0x320 +#define MC_LATENCY_ALLOWANCE_MPCORELP 0x324 +#define MC_LATENCY_ALLOWANCE_MPE_0 0x328 +#define MC_LATENCY_ALLOWANCE_MPE_1 0x32c +#define MC_LATENCY_ALLOWANCE_MPE_2 0x330 +#define MC_LATENCY_ALLOWANCE_NV_0 0x334 +#define MC_LATENCY_ALLOWANCE_NV_1 0x338 +#define MC_LATENCY_ALLOWANCE_NV2_0 0x33c +#define MC_LATENCY_ALLOWANCE_NV2_1 0x340 +#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344 +#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348 +#define MC_LATENCY_ALLOWANCE_PTC 0x34c +#define MC_LATENCY_ALLOWANCE_SATA 0x350 +#define MC_LATENCY_ALLOWANCE_VDE_0 0x354 +#define MC_LATENCY_ALLOWANCE_VDE_1 0x358 +#define MC_LATENCY_ALLOWANCE_VDE_2 0x35c +#define MC_LATENCY_ALLOWANCE_VDE_3 0x360 +#define MC_LATENCY_ALLOWANCE_VI_0 0x364 +#define MC_LATENCY_ALLOWANCE_VI_1 0x368 +#define MC_LATENCY_ALLOWANCE_VI_2 0x36c + #define MC_RESERVED_RSV 0x3fc #endif |