diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-03-31 23:18:11 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:30 -0800 |
| commit | a23e89a919c2e95bb2e690312452e346de99b37e (patch) | |
| tree | f0339521890de2079587382b880b1ee8016a8959 /arch/arm/mach-tegra/tegra3_emc.h | |
| parent | fe07bfffdeb965828a4bee4a78d1354335a5a899 (diff) | |
ARM: tegra: clock: Updated EMC clock change procedure
Original-Change-Id: I0fad4b8d931b92c8dbbdd3b6ce7dd63b42c6464f
Reviewed-on: http://git-master/r/25177
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I109a5cff6b53cfea4b48b20c9114aa4a1c02f1d8
Rebase-Id: R6416c2a2c2c1dc1fd8619842b91fea24ae10b675
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_emc.h')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_emc.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra3_emc.h b/arch/arm/mach-tegra/tegra3_emc.h index c55214e95ebd..e4d40dd500e6 100644 --- a/arch/arm/mach-tegra/tegra3_emc.h +++ b/arch/arm/mach-tegra/tegra3_emc.h @@ -51,6 +51,16 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size); #define EMC_CFG_PERIODIC_QRST (0x1 << 21) #define EMC_CFG_DYN_SREF_ENABLE (0x1 << 28) +#define EMC_REFCTRL 0x20 +#define EMC_REFCTRL_DEV_SEL_SHIFT 0 +#define EMC_REFCTRL_DEV_SEL_MASK (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT) +#define EMC_REFCTRL_ENABLE (0x1 << 31) +#define EMC_REFCTRL_ENABLE_ALL(num) \ + ((((num > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \ + | EMC_REFCTRL_ENABLE) +#define EMC_REFCTRL_DISABLE_ALL(num) \ + (((num > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) + #define EMC_TIMING_CONTROL 0x28 #define EMC_RC 0x2c #define EMC_RFC 0x30 @@ -89,7 +99,14 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size); #define EMC_ODT_READ 0xb4 #define EMC_WEXT 0xb8 #define EMC_CTT 0xbc + #define EMC_MRS_WAIT_CNT 0xc8 +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ + (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) +#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 +#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ + (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) #define EMC_MRS 0xcc #define EMC_MODE_SET_DLL_RESET (0x1 << 8) @@ -111,6 +128,7 @@ enum { #define EMC_MRW 0xe8 #define EMC_MRR 0xec #define EMC_XM2DQSPADCTRL3 0xf8 +#define EMC_XM2DQSPADCTRL3_VREF_ENABLE (0x1 << 5) #define EMC_FBIO_CFG5 0x104 #define EMC_CFG5_TYPE_SHIFT 0x0 @@ -160,6 +178,7 @@ enum { #define EMC_XM2CMDPADCTRL 0x2f0 #define EMC_XM2DQSPADCTRL2 0x2fc +#define EMC_XM2DQSPADCTRL2_VREF_ENABLE (0x1 << 5) #define EMC_XM2DQPADCTRL2 0x304 #define EMC_XM2CLKPADCTRL 0x308 #define EMC_XM2COMPPADCTRL 0x30c |