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authorDiwakar Tundlam <dtundlam@nvidia.com>2011-11-14 15:16:15 -0800
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:50:25 -0800
commit84a2d67dc80fe536d894854b7e29b6614accbfb5 (patch)
treed1297864c1bd0a27c832eb06fdea981249810652 /arch/arm/mach-tegra/tegra3_speedo.c
parentaf824e9cdd139d284b99caeab75417ab56912a54 (diff)
ARM: tegra: dvfs: Tegra3 xL support - SKUs and speedos
Bug 841336 Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com> (cherry picked from commit 92a342487a7bfe68d3c3366bbcd74c44a59f94d6) (cherry picked from commit 5f0a23567f1acfd07325f324d41cea50eab84d80) Change-Id: I793e427c7f738722786c6dd3d29411c75be50f93 Reviewed-on: http://git-master/r/67013 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Rebase-Id: R7e187fc24adac12f7a91790b74102578ed320e89
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_speedo.c')
-rw-r--r--arch/arm/mach-tegra/tegra3_speedo.c38
1 files changed, 33 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c
index c24daba2aba2..a0307ba33682 100644
--- a/arch/arm/mach-tegra/tegra3_speedo.c
+++ b/arch/arm/mach-tegra/tegra3_speedo.c
@@ -50,6 +50,10 @@ static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
{180}, /* [7]: soc_speedo_id = 1 - AP33 */
{208}, /* [8]: soc_speedo_id = 2 - T33 */
{192}, /* [9]: soc_speedo_id = 2 - T33S */
+
+/* T30 'L' family */
+ {192}, /* [10]: soc_speedo_id 2: T30L */
+ {192}, /* [11]: soc_speedo_id 2: T30SL */
};
/* Maximum speedo levels for each CPU process corner */
@@ -69,8 +73,12 @@ static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
/* T33 family */
{305, 337, 359, 376, UINT_MAX}, /* [7]: cpu_speedo_id = 4 - AP33 */
- {368, 368, 368, 368, 392}, /* [8]: cpu_speedo_id = 5 - T33 */
- {376, 376, 376, 376, 392}, /* [9]: cpu_speedo_id = 6 - T33S */
+ {368, 368, 368, 368, 392}, /* [8]: cpu_speedo_id = 5 - T33 */
+ {376, 376, 376, 376, 392}, /* [9]: cpu_speedo_id = 6 - T33S */
+
+/* T30 'L' family */
+ {305, 337, 359, 376, 392}, /* [10]: cpu_speedo_id 7: T30L */
+ {305, 337, 359, 376, 392}, /* [11]: cpu_speedo_id 8: T30SL */
};
/*
@@ -158,10 +166,30 @@ static void rev_sku_to_speedo_ids(int rev, int sku)
}
break;
- case 0x83: /* T30S */
- cpu_speedo_id = 3;
+ case 0x83: /* T30L or T30S */
+ switch (package_id) {
+ case 1: /* MID => T30L */
+ cpu_speedo_id = 7;
+ soc_speedo_id = 2;
+ threshold_index = 10;
+ break;
+ case 2: /* DSC => T30S */
+ cpu_speedo_id = 3;
+ soc_speedo_id = 2;
+ threshold_index = 3;
+ break;
+ default:
+ pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n",
+ package_id);
+ BUG();
+ break;
+ }
+ break;
+
+ case 0x8F: /* T30SL */
+ cpu_speedo_id = 8;
soc_speedo_id = 2;
- threshold_index = 3;
+ threshold_index = 11;
break;
/* Characterization SKUs */