diff options
| author | Daniel Solomon <daniels@nvidia.com> | 2012-01-26 15:14:34 -0800 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-02-03 05:43:54 -0800 |
| commit | ea28526cb21ea041f71da806cb91fc6739f05995 (patch) | |
| tree | 8471beeea4dcd0fccac006db3a9fe21e1d1df9af /arch/arm/mach-tegra/tegra3_speedo.c | |
| parent | 76ae82be48f2b256f55e6ddbdf00b91088b4ba3d (diff) | |
ARM: tegra: dvfs: Add Tegra3 x7 detection
- Detect T37 and AP37 SKUs.
- Created a new threshold for T37
Bug 841336
Reviewed-on: http://git-master/r/77661
Change-Id: I78a6875058ebd6bc5e70042aec020c259de0976c
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78708
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_speedo.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_speedo.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c index 325e2b7b0bc8..eae8e5e9dba6 100644 --- a/arch/arm/mach-tegra/tegra3_speedo.c +++ b/arch/arm/mach-tegra/tegra3_speedo.c @@ -58,6 +58,9 @@ static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { /* T30 Automotives */ {185}, /* [12]: soc_speedo_id = 3 - Automotives */ {185}, /* [13]: soc_speedo_id = 3 - Automotives */ + +/* T37 Family*/ + {220}, /* [14]: soc_speedo_id 2: T37 */ }; /* Maximum speedo levels for each CPU process corner */ @@ -91,6 +94,9 @@ static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = { */ {300, 311, 360, 371, 381, 415, 431}, {300, 311, 410, 431, UINT_MAX}, /* threshold_index 13: cpu_speedo_id = 11 */ + +/* T37 family */ + {368, 368, 368, 368, 392, UINT_MAX}, /* [14]: cpu_speedo_id = 13 - T37 */ }; /* @@ -204,6 +210,26 @@ static void rev_sku_to_speedo_ids(int rev, int sku) threshold_index = 11; break; + case 0xA0: /* T37 or A37 */ + switch (package_id) { + case 1: /* MID => T37 */ + cpu_speedo_id = 13; + soc_speedo_id = 2; + threshold_index = 14; + break; + case 2: /* DSC => AP37 */ + cpu_speedo_id = 12; + soc_speedo_id = 2; + threshold_index = 9; + break; + default: + pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n", + package_id); + BUG(); + break; + } + break; + /* Characterization SKUs */ case 0x08: /* AP30 char */ cpu_speedo_id = 1; |