diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2011-05-12 09:44:45 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:43 -0800 |
| commit | cbb71973b3a6882596bfb6dc7a181c5ce4f27a63 (patch) | |
| tree | 0e1a76a90f7b1231a03864cbe481805f879c8383 /arch/arm/mach-tegra/tegra3_speedo.c | |
| parent | 07fc331f7ca9eb8b6c4958cafb302b0e9def78bd (diff) | |
ARM: tegra: clocks: sku limit for pclk
sclk max rate for AP25 is 300MHz and pclk is set as 1:2 to sclk.
pclk max rate changed to 150MHz for AP25.
Bug 821534
Reviewed-on: http://git-master/r/31311
(cherry picked from commit 3655e9a4940bfa39ba103903f2e2f1d5f0cf7e2d)
Original-Change-Id: Id10c322892e646c2c1f74cbf36268608fc268493
Reviewed-on: http://git-master/r/32874
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: R7b21164fa84f78febf445ce4b60e92b1d70c6406
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_speedo.c')
0 files changed, 0 insertions, 0 deletions