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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2014-12-18 05:32:28 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2014-12-18 05:32:28 +0100 |
| commit | 18d5f4a85d71d7921e9b121aeefb9c12c888d781 (patch) | |
| tree | 9d4db4ca68a4aefea6007cf02223aa24630dada2 /arch/arm/mach-tegra/tegra3_usb_phy.c | |
| parent | 45c163d2da4d3fae3f555bd91d68d6043d2c1f7b (diff) | |
video: tegra: fb: fix pixel clock polarity
The pixel clock polarity setting was wrong: The kernel display flags
are rather somewhat confusing: The flags specify the edge where the
data should be driven by the controller (and hence not sampled by the
display!).
Please note that we don't change the default pixel clock polarity.
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_usb_phy.c')
0 files changed, 0 insertions, 0 deletions