diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-03-28 00:19:32 -0700 |
|---|---|---|
| committer | Yu-Huan Hsu <yhsu@nvidia.com> | 2014-03-28 13:54:44 -0700 |
| commit | 36c0a3c6c6e406ea606c5785bec09e2944398d36 (patch) | |
| tree | ad6c7997d2bf4fa41250a92034386fba51e1ee6c /arch/arm/mach-tegra/tegra_cl_dvfs.c | |
| parent | bbcf473daa62296808d21f24bb6dd22dcbc7e9e6 (diff) | |
ARM: tegra: dvfs: Add delay after DFLL enable
Added 1us propagation delay after DFLL is enabled in open loop mode
as a double-precaution on top of already inserted memory barrier and
read fence.
Change-Id: Iab6a61833b5ef087c8f4da57b8d78d6a571dbb9e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/389581
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra_cl_dvfs.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra_cl_dvfs.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra_cl_dvfs.c b/arch/arm/mach-tegra/tegra_cl_dvfs.c index 84d4b073d16c..b26a49a69133 100644 --- a/arch/arm/mach-tegra/tegra_cl_dvfs.c +++ b/arch/arm/mach-tegra/tegra_cl_dvfs.c @@ -2536,6 +2536,7 @@ int tegra_cl_dvfs_enable(struct tegra_cl_dvfs *cld) cl_dvfs_enable_clocks(cld); set_mode(cld, TEGRA_CL_DVFS_OPEN_LOOP); + udelay(1); return 0; } |