diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-04-01 20:10:40 -0700 |
|---|---|---|
| committer | Yu-Huan Hsu <yhsu@nvidia.com> | 2014-04-09 13:40:26 -0700 |
| commit | 8512300b08fe11c66494cbbdd64f39379091a3aa (patch) | |
| tree | 071cf22f0bb9d272adace62f5c745dcb2d2caec1 /arch/arm/mach-tegra/tegra_cl_dvfs.c | |
| parent | 0f2c38d284f65d3545ab3f4f3a13c064f7fbb626 (diff) | |
ARM: tegra: dvfs: Tune DFLL low at cold
Added an option to tune DFLL low in the entire voltage range while
temperature is below minimum trip-point; still different tuning setting
are used in low and high voltage ranges while temperature is above cold
trip-point. For now, this option is disabled on all Tegra platforms.
Bug 1492902
Change-Id: Ibf080279b034522add8eed4da15617b59ac1a59a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/391123
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra_cl_dvfs.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra_cl_dvfs.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra_cl_dvfs.c b/arch/arm/mach-tegra/tegra_cl_dvfs.c index 2183f5cfae4e..94f59aaa3cfd 100644 --- a/arch/arm/mach-tegra/tegra_cl_dvfs.c +++ b/arch/arm/mach-tegra/tegra_cl_dvfs.c @@ -698,6 +698,16 @@ static inline void tune_high(struct tegra_cl_dvfs *cld) cl_dvfs_wmb(cld); } +static inline int cl_tune_target(struct tegra_cl_dvfs *cld, u32 out_cap) +{ + bool tune_low_at_cold = cld->safe_dvfs->dfll_data.tune0_low_at_cold; + + if ((out_cap > cld->tune_high_out_start) && + (!tune_low_at_cold || cld->therm_floor_idx)) + return TEGRA_CL_DVFS_TUNE_HIGH; + return TEGRA_CL_DVFS_TUNE_LOW; +} + static void set_output_limits(struct tegra_cl_dvfs *cld, u8 out_min, u8 out_max) { seqcount_t *vmin_seqcnt = NULL; @@ -752,7 +762,7 @@ static void set_cl_config(struct tegra_cl_dvfs *cld, struct dfll_rate_req *req) switch (cld->tune_state) { case TEGRA_CL_DVFS_TUNE_LOW: - if (out_cap > cld->tune_high_out_start) { + if (cl_tune_target(cld, out_cap) > TEGRA_CL_DVFS_TUNE_LOW) { set_tune_state(cld, TEGRA_CL_DVFS_TUNE_HIGH_REQUEST); mod_timer(&cld->tune_timer, jiffies + cld->tune_delay); cl_dvfs_set_force_out_min(cld); @@ -761,7 +771,7 @@ static void set_cl_config(struct tegra_cl_dvfs *cld, struct dfll_rate_req *req) case TEGRA_CL_DVFS_TUNE_HIGH: case TEGRA_CL_DVFS_TUNE_HIGH_REQUEST: - if (out_cap <= cld->tune_high_out_start) { + if (cl_tune_target(cld, out_cap) == TEGRA_CL_DVFS_TUNE_LOW) { set_tune_state(cld, TEGRA_CL_DVFS_TUNE_LOW); tune_low(cld); cl_dvfs_set_force_out_min(cld); |