diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-04-23 17:14:00 -0700 |
|---|---|---|
| committer | Riham Haidar <rhaidar@nvidia.com> | 2014-05-16 12:02:41 -0700 |
| commit | b5adc8efaad051a87df67fa701076bd12ff2c9aa (patch) | |
| tree | e40e912874429c7b2a6ddbea286a5d90a5a80e0a /arch/arm/mach-tegra/tegra_cl_dvfs.c | |
| parent | 48293ae83aa61c1b0633977729b23e0379bf16b5 (diff) | |
ARM: tegra: dvfs: Defer calibration on force value
Deferred DFLL calibration if last sent voltage is at the initially
forced request output level. It is needed to avoid false interpretation
of high voltage when power management micro-controller re-sends DFLL
request underneath CLDVFS driver running on CPU.
Bug 1492902
Change-Id: I0757469ff432818d1aadb616accba01136345257
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/402659
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra_cl_dvfs.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra_cl_dvfs.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra_cl_dvfs.c b/arch/arm/mach-tegra/tegra_cl_dvfs.c index f6cfca034b01..8a84dbe0c181 100644 --- a/arch/arm/mach-tegra/tegra_cl_dvfs.c +++ b/arch/arm/mach-tegra/tegra_cl_dvfs.c @@ -957,6 +957,13 @@ static void cl_dvfs_calibrate(struct tegra_cl_dvfs *cld) } } + /* Defer if we are still sending request force_val - possible when + request updated outside this driver by CPU internal pm controller */ + if (val == cld->last_req.output) { + calibration_timer_update(cld); + return; + } + /* Adjust minimum rate */ rate = GET_MONITORED_RATE(data, cld->ref_rate); if ((val > out_min) || (rate < (rate_min - step))) |