diff options
| author | Alex Frid <afrid@nvidia.com> | 2013-12-10 15:25:40 -0800 |
|---|---|---|
| committer | Yu-Huan Hsu <yhsu@nvidia.com> | 2013-12-11 15:08:18 -0800 |
| commit | d74590ea96bb1e0d1309843977f3e6564e593041 (patch) | |
| tree | e40d41eda9ec4c89339b8b7f6e0e5627c80458e1 /arch/arm/mach-tegra/tegra_cl_dvfs.c | |
| parent | e8cfbdc1452262691058f57a35c208863fe164a2 (diff) | |
ARM: tegra: dvfs: Fix DFLL voltage mapping
Fixed DFLL voltages mapping when maximum voltage is reached by the
frequency below the top one: map all the rest frequencies to maximum
DFLL output.
Bug 1422196
Change-Id: I58394fe54cd6b3196c8adfac911a812b1c4cca1e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/343868
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra_cl_dvfs.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra_cl_dvfs.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra_cl_dvfs.c b/arch/arm/mach-tegra/tegra_cl_dvfs.c index 543298efe17e..ab2b65ac65bc 100644 --- a/arch/arm/mach-tegra/tegra_cl_dvfs.c +++ b/arch/arm/mach-tegra/tegra_cl_dvfs.c @@ -1072,6 +1072,10 @@ static void cl_dvfs_init_maps(struct tegra_cl_dvfs *cld) break; } cld->num_voltages = j; + + /* hit Vmax before last freq was mapped: map the rest to max output */ + for (j = i++; i < n; i++) + cld->clk_dvfs_map[i] = cld->clk_dvfs_map[j]; } static void cl_dvfs_init_tuning_thresholds(struct tegra_cl_dvfs *cld) |