diff options
author | Scott Williams <scwilliams@nvidia.com> | 2011-03-14 15:24:46 -0700 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:27 -0800 |
commit | c651302494cbdeb2e6e55c57581429ad7a81bf87 (patch) | |
tree | 6fe424dd2ee258150124ae0659ab03df62376df7 /arch/arm/mach-tegra/timer-t3.c | |
parent | 8f151d18b7b225b4be37beb2b166ca8ef093c61e (diff) |
arm: tegra: timer: New Tegra3 IRQ mapping
Rename timer.c to timer-t2.c for consistency with other
chip-specific implementations.
Bug 790458
Bug 790448
Bug 738259
Original-Change-Id: I7e0fceb716590cd92b64ba00c0bebe659e9beb21
Reviewed-on: http://git-master/r/22885
Tested-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I322324c2177d57657a63e9428f8e49d5df2b828e
Rebase-Id: R7312866cdc8044a71cc2f83ad4bc7aa66b07416d
Diffstat (limited to 'arch/arm/mach-tegra/timer-t3.c')
-rw-r--r-- | arch/arm/mach-tegra/timer-t3.c | 50 |
1 files changed, 35 insertions, 15 deletions
diff --git a/arch/arm/mach-tegra/timer-t3.c b/arch/arm/mach-tegra/timer-t3.c index 66d51635002c..629438869bf7 100644 --- a/arch/arm/mach-tegra/timer-t3.c +++ b/arch/arm/mach-tegra/timer-t3.c @@ -62,12 +62,12 @@ #define TIMERUS_USEC_CFG 0x14 #define TIMERUS_CNTR_FREEZE 0x4c -#define TIMER1_BASE 0x0 -#define TIMER2_BASE 0x8 -#define TIMER3_BASE 0x50 -#define TIMER4_BASE 0x58 -#define TIMER5_BASE 0x60 -#define TIMER6_BASE 0x68 +#define TIMER1_OFFSET (TEGRA_TMR1_BASE-TEGRA_TMR1_BASE) +#define TIMER2_OFFSET (TEGRA_TMR2_BASE-TEGRA_TMR1_BASE) +#define TIMER3_OFFSET (TEGRA_TMR3_BASE-TEGRA_TMR1_BASE) +#define TIMER4_OFFSET (TEGRA_TMR4_BASE-TEGRA_TMR1_BASE) +#define TIMER5_OFFSET (TEGRA_TMR5_BASE-TEGRA_TMR1_BASE) +#define TIMER6_OFFSET (TEGRA_TMR6_BASE-TEGRA_TMR1_BASE) #define TIMER_PTV 0x0 #define TIMER_PCR 0x4 @@ -90,7 +90,7 @@ static int tegra_timer_set_next_event(unsigned long cycles, u32 reg; reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); - timer_writel(reg, TIMER1_BASE + TIMER_PTV); + timer_writel(reg, TIMER1_OFFSET + TIMER_PTV); return 0; } @@ -100,12 +100,12 @@ static void tegra_timer_set_mode(enum clock_event_mode mode, { u32 reg; - timer_writel(0, TIMER1_BASE + TIMER_PTV); + timer_writel(0, TIMER1_OFFSET + TIMER_PTV); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: reg = 0xC0000000 | ((1000000/HZ)-1); - timer_writel(reg, TIMER1_BASE + TIMER_PTV); + timer_writel(reg, TIMER1_OFFSET + TIMER_PTV); break; case CLOCK_EVT_MODE_ONESHOT: break; @@ -198,7 +198,7 @@ void read_persistent_clock(struct timespec *ts) static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = (struct clock_event_device *)dev_id; - timer_writel(1<<30, TIMER1_BASE + TIMER_PCR); + timer_writel(1<<30, TIMER1_OFFSET + TIMER_PCR); evt->event_handler(evt); return IRQ_HANDLED; } @@ -212,10 +212,10 @@ static struct irqaction tegra_timer_irq = { }; static int lp2_wake_timers[] = { - TIMER3_BASE, - TIMER4_BASE, - TIMER5_BASE, - TIMER6_BASE, + TIMER3_OFFSET, + TIMER4_OFFSET, + TIMER5_OFFSET, + TIMER6_OFFSET, }; static irqreturn_t tegra_lp2wake_interrupt(int irq, void *dev_id) @@ -241,7 +241,7 @@ static struct irqaction tegra_lp2wake_irq_cpu##n = { \ LP2_TIMER_IRQ_ACTION(0, INT_TMR3); \ LP2_TIMER_IRQ_ACTION(1, INT_TMR4); \ LP2_TIMER_IRQ_ACTION(2, INT_TMR5); \ - LP2_TIMER_IRQ_ACTION(3, INT_TMR_SHARED); + LP2_TIMER_IRQ_ACTION(3, INT_TMR6); LP2_TIMER_IRQ_ACTIONS(); @@ -296,6 +296,8 @@ static void test_lp2_wake_timers(void){} static void __init tegra_init_timer(void) { unsigned long rate = clk_measure_input_freq(); + void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804; + unsigned long id; int ret; #ifdef CONFIG_HAVE_ARM_TWD @@ -339,6 +341,24 @@ static void __init tegra_init_timer(void) BUG(); } + /* For T30.A01 use INT_TMR_SHARED instead of INT_TMR6. */ + id = readl(chip_id); + if (((id & 0xFF00) >> 8) == 0x30) { +#ifndef CONFIG_TEGRA_FPGA_PLATFORM + if (((id >> 16) & 0xf) == 1) { + tegra_lp2wake_irq_cpu3.irq = INT_TMR_SHARED; + } +#else + void __iomem *emu_rev = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x860; + unsigned long reg = readl(emu_rev); + unsigned long netlist = reg & 0xFFFF; + unsigned long patch = (reg >> 16) & 0xFF; + if ((netlist == 12) && (patch < 14)) { + tegra_lp2wake_irq_cpu3.irq = INT_TMR_SHARED; + } +#endif + } + REGISTER_LP2_WAKE_IRQS(); clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5); |