ARM: tegra: e1853: Add board support for e1853

E1853 is T30 based Automotive platform.

Changes done:
1. New board specific files added
2. Added new machine number for E1853
3. Added pinmux configuration for E1853

Bug 966833
Bug 1018258

Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>

Change-Id: Ibf1093f59e10a0a5cfa42a177c21c0db01983196
Reviewed-on: http://git-master/r/118000
Tested-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
(cherry picked from commit ad9dd1b3242f23c0f46eaf92ab49f495c06f330f)
Reviewed-on: http://git-master/r/119580
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 files changed, 1206 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/board-e1853-panel.c b/arch/arm/mach-tegra/board-e1853-panel.c
new file mode 100644
index 000000000000..1e6c7ab60907
--- /dev/null
+++ b/arch/arm/mach-tegra/board-e1853-panel.c
@@ -0,0 +1,146 @@
+/*
+ * arch/arm/mach-tegra/board-e1853-panel.c
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/resource.h>
+#include <asm/mach-types.h>
+#include <linux/platform_device.h>
+#include <linux/nvhost.h>
+#include <linux/nvmap.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/dc.h>
+#include <mach/fb.h>
+
+#include "board.h"
+#include "devices.h"
+#include "tegra3_host1x_devices.h"
+
+static int e1853_panel_enable(void)
+{
+	return 0;
+}
+
+static int e1853_panel_disable(void)
+{
+	return 0;
+}
+
+static struct tegra_dc_mode e1853_panel_modes[] = {
+	{
+		/* 800x480@60 */
+		.pclk = 32460000,
+		.h_ref_to_sync = 1,
+		.v_ref_to_sync = 1,
+		.h_sync_width = 64,
+		.v_sync_width = 3,
+		.h_back_porch = 128,
+		.v_back_porch = 22,
+		.h_front_porch = 64,
+		.v_front_porch = 20,
+		.h_active = 800,
+		.v_active = 480,
+	},
+};
+
+static struct tegra_fb_data e1853_fb_data = {
+	.win		= 0,
+	.xres		= 800,
+	.yres		= 480,
+	.bits_per_pixel	= 32,
+};
+
+static struct tegra_dc_out e1853_disp1_out = {
+	.align		= TEGRA_DC_ALIGN_MSB,
+	.order		= TEGRA_DC_ORDER_RED_BLUE,
+	.type		= TEGRA_DC_OUT_RGB,
+	.modes		= e1853_panel_modes,
+	.n_modes	= ARRAY_SIZE(e1853_panel_modes),
+	.enable		= e1853_panel_enable,
+	.disable	= e1853_panel_disable,
+};
+
+static struct tegra_dc_platform_data e1853_disp1_pdata = {
+	.flags		= TEGRA_DC_FLAG_ENABLED,
+	.default_out	= &e1853_disp1_out,
+	.emc_clk_rate	= 300000000,
+	.fb		= &e1853_fb_data,
+};
+
+static struct nvmap_platform_carveout e1853_carveouts[] = {
+	[0] = {
+		.name		= "iram",
+		.usage_mask	= NVMAP_HEAP_CARVEOUT_IRAM,
+		.base		= TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
+		.size		= TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
+		.buddy_size	= 0, /* no buddy allocation for IRAM */
+	},
+	[1] = {
+		.name		= "generic-0",
+		.usage_mask	= NVMAP_HEAP_CARVEOUT_GENERIC,
+		.base		= 0,	/* Filled in by e1853_panel_init() */
+		.size		= 0,	/* Filled in by e1853_panel_init() */
+		.buddy_size	= SZ_32K,
+	},
+};
+
+static struct nvmap_platform_data e1853_nvmap_data = {
+	.carveouts	= e1853_carveouts,
+	.nr_carveouts	= ARRAY_SIZE(e1853_carveouts),
+};
+
+static struct platform_device *e1853_gfx_devices[] __initdata = {
+	&tegra_nvmap_device,
+};
+
+int __init e1853_panel_init(void)
+{
+	int err;
+	struct resource *res;
+
+	e1853_carveouts[1].base = tegra_carveout_start;
+	e1853_carveouts[1].size = tegra_carveout_size;
+	tegra_nvmap_device.dev.platform_data = &e1853_nvmap_data;
+	tegra_disp1_device.dev.platform_data = &e1853_disp1_pdata;
+
+	res = nvhost_get_resource_byname(&tegra_disp1_device,
+					 IORESOURCE_MEM, "fbmem");
+	if (!res) {
+		pr_err("No memory resources\n");
+		return -ENODEV;
+	}
+	res->start = tegra_fb_start;
+	res->end = tegra_fb_start + tegra_fb_size - 1;
+
+#ifdef CONFIG_TEGRA_GRHOST
+	err = tegra3_register_host1x_devices();
+	if (err)
+		return err;
+#endif
+
+	err = platform_add_devices(e1853_gfx_devices,
+				ARRAY_SIZE(e1853_gfx_devices));
+	if (!err)
+		err = nvhost_device_register(&tegra_disp1_device);
+
+#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP)
+	if (!err)
+		err = nvhost_device_register(&nvavp_device);
+#endif
+	return err;
+}
diff --git a/arch/arm/mach-tegra/board-e1853-pinmux.c b/arch/arm/mach-tegra/board-e1853-pinmux.c
new file mode 100644
index 000000000000..3f25291609fe
--- /dev/null
+++ b/arch/arm/mach-tegra/board-e1853-pinmux.c
@@ -0,0 +1,503 @@
+/*
+ * arch/arm/mach-tegra/board-e1853-pinmux.c
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <mach/pinmux.h>
+#include <linux/gpio.h>
+#include "board.h"
+#include "board-e1853.h"
+#include "gpio-names.h"
+
+#define DEFAULT_DRIVE(_name)					\
+	{							\
+		.pingroup = TEGRA_DRIVE_PINGROUP_##_name,	\
+		.hsm = TEGRA_HSM_DISABLE,			\
+		.schmitt = TEGRA_SCHMITT_ENABLE,		\
+		.drive = TEGRA_DRIVE_DIV_1,			\
+		.pull_down = TEGRA_PULL_31,			\
+		.pull_up = TEGRA_PULL_31,			\
+		.slew_rising = TEGRA_SLEW_SLOWEST,		\
+		.slew_falling = TEGRA_SLEW_SLOWEST,		\
+	}
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ *                strength code. Value from 0 to 31.
+ * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
+ *                strength code. Value from 0 to 31.
+ * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew -  Driver Output Pull-Down slew control code -
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ */
+#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
+	{                                               \
+		.pingroup = TEGRA_DRIVE_PINGROUP_##_name,   \
+		.hsm = TEGRA_HSM_##_hsm,                    \
+		.schmitt = TEGRA_SCHMITT_##_schmitt,        \
+		.drive = TEGRA_DRIVE_##_drive,              \
+		.pull_down = TEGRA_PULL_##_pulldn_drive,    \
+		.pull_up = TEGRA_PULL_##_pullup_drive,		\
+		.slew_rising = TEGRA_SLEW_##_pulldn_slew,   \
+		.slew_falling = TEGRA_SLEW_##_pullup_slew,	\
+	}
+
+/* !!!FIXME!!!!  Update drive strength with characterized value  */
+static __initdata struct tegra_drive_pingroup_config e1853_drive_pinmux[] = {
+	/* ATC1 CFG */
+	SET_DRIVE(AT1,	ENABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST),
+	/* ATC2 CFG */
+	SET_DRIVE(AT2,	ENABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST),
+	/* ATC3 CFG */
+	SET_DRIVE(AT3,	ENABLE, ENABLE, DIV_1, 0, 0, SLOWEST, SLOWEST),
+	/* ATC4 CFG */
+	SET_DRIVE(AT4,	DISABLE, DISABLE, DIV_1, 0, 0, SLOWEST, SLOWEST),
+
+	/* All I2C pins are driven to maximum drive strength */
+	/* GEN1 I2C */
+	SET_DRIVE(DBG,	DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+	/* GEN2 I2C */
+	SET_DRIVE(AT5,	DISABLE, ENABLE, DIV_1, 12, 30, FASTEST, FASTEST),
+
+	/* DDC I2C */
+	SET_DRIVE(DDC,	DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+	/* PWR_I2C */
+	SET_DRIVE(AO1,	DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+	/* SDMMC4 */
+	SET_DRIVE(GME,	DISABLE, ENABLE, DIV_1, 22, 18, SLOWEST, SLOWEST),
+	SET_DRIVE(GMF,	DISABLE, ENABLE, DIV_1,  0,  0, SLOWEST, SLOWEST),
+	SET_DRIVE(GMG,	DISABLE, ENABLE, DIV_1, 15,  6, SLOWEST, SLOWEST),
+	SET_DRIVE(GMH,	DISABLE, ENABLE, DIV_1, 12,  6, SLOWEST, SLOWEST),
+
+	/* LCD */
+	SET_DRIVE(LCD1,	DISABLE, ENABLE, DIV_1, 31,  31, FASTEST, FASTEST),
+	SET_DRIVE(LCD2,	DISABLE, ENABLE, DIV_1,  2,   2, FASTEST, FASTEST),
+
+	/* DAP2 */
+	SET_DRIVE(DAP2,	ENABLE, ENABLE, DIV_1, 0,  0, SLOWEST, SLOWEST),
+	/* DAP4 */
+	SET_DRIVE(DAP4,	ENABLE, ENABLE, DIV_1, 0,  0, SLOWEST, SLOWEST),
+	/* DBG */
+	SET_DRIVE(DBG,	ENABLE, ENABLE, DIV_1, 20,  0, SLOWEST, SLOWEST),
+	/* SPI */
+	SET_DRIVE(SPI,	ENABLE, ENABLE, DIV_1, 0,  0, SLOWEST, SLOWEST),
+	/* UAA */
+	SET_DRIVE(UAA,	DISABLE, DISABLE, DIV_1, 0,  0, SLOWEST, SLOWEST),
+	/* UART2 */
+	SET_DRIVE(UART2,	ENABLE, ENABLE, DIV_1, 0,  0, SLOWEST, SLOWEST),
+	/* UART3 */
+	SET_DRIVE(UART3,	ENABLE, ENABLE, DIV_1, 0,  0, SLOWEST, SLOWEST),
+	/* GME */
+	SET_DRIVE(GME,	DISABLE, ENABLE, DIV_1, 1,  4, SLOWEST, SLOWEST),
+	/* GMF */
+	SET_DRIVE(GMF,	DISABLE, ENABLE, DIV_1, 0,  0, SLOWEST, SLOWEST),
+	/* GMG */
+	SET_DRIVE(GMG,	DISABLE, ENABLE, DIV_1, 3,  0, SLOWEST, SLOWEST),
+	/* GMH */
+	SET_DRIVE(GMH,	DISABLE, ENABLE, DIV_1, 0,  12, SLOWEST, SLOWEST),
+
+	/* I2S/TDM */
+#ifdef CONFIG_TEGRA_MODS
+	SET_DRIVE(DAP1,	ENABLE, ENABLE, DIV_1, 20,  20, SLOWEST, SLOWEST),
+	SET_DRIVE(DAP3,	ENABLE, ENABLE, DIV_1, 20,  20, SLOWEST, SLOWEST),
+#else
+	SET_DRIVE(DAP1,	ENABLE, ENABLE, DIV_1, 3,  3, SLOWEST, SLOWEST),
+	SET_DRIVE(DAP3,	ENABLE, ENABLE, DIV_1, 3,  3, SLOWEST, SLOWEST),
+#endif
+
+	/* SPI */
+	SET_DRIVE(UAD,		DISABLE, ENABLE, DIV_1, 4, 1, SLOWEST, SLOWEST),
+	SET_DRIVE(UAB,		DISABLE, ENABLE, DIV_1, 4, 1, SLOWEST, SLOWEST),
+
+	/* SDMMC 3 */
+	SET_DRIVE(SDIO3,	DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST),
+};
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io)	\
+	{							\
+		.pingroup	= TEGRA_PINGROUP_##_pingroup,	\
+		.func		= TEGRA_MUX_##_mux,		\
+		.pupd		= TEGRA_PUPD_##_pupd,		\
+		.tristate	= TEGRA_TRI_##_tri,		\
+		.io		= TEGRA_PIN_##_io,		\
+		.lock		= TEGRA_PIN_LOCK_DEFAULT,	\
+		.od		= TEGRA_PIN_OD_DEFAULT,		\
+		.ioreset	= TEGRA_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
+	{							\
+		.pingroup	= TEGRA_PINGROUP_##_pingroup,	\
+		.func		= TEGRA_MUX_##_mux,		\
+		.pupd		= TEGRA_PUPD_##_pupd,		\
+		.tristate	= TEGRA_TRI_##_tri,		\
+		.io		= TEGRA_PIN_##_io,		\
+		.lock		= TEGRA_PIN_LOCK_##_lock,	\
+		.od		= TEGRA_PIN_OD_##_od,		\
+		.ioreset	= TEGRA_PIN_IO_RESET_DEFAULT,	\
+	}
+
+#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
+	{							\
+		.pingroup	= TEGRA_PINGROUP_##_pingroup,	\
+		.func		= TEGRA_MUX_##_mux,		\
+		.pupd		= TEGRA_PUPD_##_pupd,		\
+		.tristate	= TEGRA_TRI_##_tri,		\
+		.io		= TEGRA_PIN_##_io,		\
+		.lock		= TEGRA_PIN_LOCK_##_lock,	\
+		.od		= TEGRA_PIN_OD_DEFAULT,		\
+		.ioreset	= TEGRA_PIN_IO_RESET_##_ioreset	\
+	}
+
+static __initdata struct tegra_pingroup_config e1853_pinmux_common[] = {
+
+	/* CLK-EXTCLK1 */
+	DEFAULT_PINMUX(CLK1_OUT,	EXTPERIPH1,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(CLK3_OUT,	EXTPERIPH3,	NORMAL,		NORMAL,		OUTPUT),
+
+	/* SDMMC1 pinmux */
+	DEFAULT_PINMUX(SDMMC1_CLK,	SDMMC1,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC1_CMD,	SDMMC1,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT3,	SDMMC1,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT2,	SDMMC1,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT1,	SDMMC1,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC1_DAT0,	SDMMC1,		PULL_UP,	NORMAL,		INPUT),
+
+	/* SDMMC2 pinmux */
+	DEFAULT_PINMUX(KB_ROW10,	SDMMC2,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(KB_ROW11,	SDMMC2,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(KB_ROW12,	SDMMC2,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(KB_ROW13,	SDMMC2,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(KB_ROW14,	SDMMC2,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(KB_ROW15,	SDMMC2,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(KB_ROW6,		SDMMC2,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(KB_ROW7,		SDMMC2,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(KB_ROW8,		SDMMC2,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(KB_ROW9,		SDMMC2,		PULL_UP,	NORMAL,		INPUT),
+
+	/* SDMMC3 pinmux */
+	DEFAULT_PINMUX(SDMMC3_CLK,	SDMMC3,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC3_CMD,	SDMMC3,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT0,	SDMMC3,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT1,	SDMMC3,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT2,	SDMMC3,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT3,	SDMMC3,		PULL_UP,	NORMAL,		INPUT),
+
+	/* I2C1 pinmux */
+	I2C_PINMUX(GEN1_I2C_SCL,	I2C1,		NORMAL,		NORMAL,		INPUT,		DISABLE,	ENABLE),
+	I2C_PINMUX(GEN1_I2C_SDA,	I2C1,		NORMAL,		NORMAL,		INPUT,		DISABLE,	ENABLE),
+
+	/* I2C2 pinmux */
+	I2C_PINMUX(GEN2_I2C_SCL,	I2C2,		NORMAL,		NORMAL,		INPUT,		DISABLE,	ENABLE),
+	I2C_PINMUX(GEN2_I2C_SDA,	I2C2,		NORMAL,		NORMAL,		INPUT,		DISABLE,	ENABLE),
+
+	/* I2C3 pinmux */
+	I2C_PINMUX(CAM_I2C_SCL,		I2C3,		PULL_UP,	NORMAL,		INPUT,		DISABLE,	ENABLE),
+	I2C_PINMUX(CAM_I2C_SDA,		I2C3,		PULL_UP,	NORMAL,		INPUT,		DISABLE,	ENABLE),
+
+	/* I2C4 pinmux */
+	I2C_PINMUX(DDC_SCL,		I2C4,		NORMAL,		NORMAL,		INPUT,		DISABLE,	ENABLE),
+	I2C_PINMUX(DDC_SDA,		I2C4,		NORMAL,		NORMAL,		INPUT,		DISABLE,	ENABLE),
+
+	/* PowerI2C pinmux */
+	I2C_PINMUX(PWR_I2C_SCL,		I2CPWR,		NORMAL,		NORMAL,		INPUT,		DISABLE,	ENABLE),
+	I2C_PINMUX(PWR_I2C_SDA,		I2CPWR,		NORMAL,		NORMAL,		INPUT,		DISABLE,	ENABLE),
+
+	/* UART1 pinmux */
+	DEFAULT_PINMUX(GPIO_PU0,	UARTA,		PULL_UP,	NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU1,	UARTA,		NORMAL,		NORMAL,		INPUT),
+
+	/* UART2 pinmux */
+	DEFAULT_PINMUX(UART2_CTS_N,	UARTB,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(UART2_RTS_N,	UARTB,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(UART2_RXD,	IRDA,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(UART2_TXD,	IRDA,		PULL_UP,	NORMAL,		OUTPUT),
+
+	/* UART3 pinmux */
+	DEFAULT_PINMUX(UART3_CTS_N,	UARTC,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(UART3_RTS_N,	UARTC,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(UART3_RXD,	UARTC,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(UART3_TXD,	UARTC,		PULL_UP,	NORMAL,		OUTPUT),
+
+	/* UART4 pinmux */
+	DEFAULT_PINMUX(ULPI_CLK,	UARTD,		PULL_UP,	NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(ULPI_DIR,	UARTD,		NORMAL,		NORMAL,		INPUT),
+
+	/* SPI2 pinmux */
+	DEFAULT_PINMUX(ULPI_DATA4,	SPI2,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(ULPI_DATA5,	SPI2,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(ULPI_DATA6,	SPI2,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(ULPI_DATA7,	SPI2,		NORMAL,		NORMAL,		INPUT),
+
+	/* SPI3 pinmux */
+	DEFAULT_PINMUX(ULPI_DATA0,	SPI3,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(ULPI_DATA1,	SPI3,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(ULPI_DATA2,	SPI3,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(ULPI_DATA3,	SPI3,		NORMAL,		NORMAL,		INPUT),
+
+	/* SPI5 pinmux */
+	DEFAULT_PINMUX(LCD_SCK,		SPI5,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(LCD_CS0_N,	SPI5,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(LCD_SDIN,	SPI5,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(LCD_SDOUT,	SPI5,		NORMAL,		NORMAL,		INPUT),
+
+	/* DAP1 */
+	DEFAULT_PINMUX(DAP1_FS,		I2S0,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(DAP1_DIN,	I2S0,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(DAP1_DOUT,	I2S0,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(DAP1_SCLK,	I2S0,		NORMAL,		NORMAL,		INPUT),
+
+	/* DAP2 */
+	DEFAULT_PINMUX(DAP3_FS,		I2S2,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(DAP3_DIN,	I2S2,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(DAP3_DOUT,	I2S2,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(DAP3_SCLK,	I2S2,		NORMAL,		NORMAL,		INPUT),
+
+	/* I2S1 */
+	DEFAULT_PINMUX(DAP2_DIN,	I2S1,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(DAP2_DOUT,	I2S1,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(DAP2_FS,		I2S1,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(DAP2_SCLK,	I2S1,		NORMAL,		NORMAL,		INPUT),
+
+	/* I2S3 */
+	DEFAULT_PINMUX(DAP4_DIN,	I2S3,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(DAP4_DOUT,	I2S3,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(DAP4_FS,		I2S3,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(DAP4_SCLK,	I2S3,		NORMAL,		NORMAL,		INPUT),
+
+	/* NOR pinmux */
+	DEFAULT_PINMUX(SDMMC4_DAT0,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT1,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT2,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT3,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT4,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT5,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC4_DAT6,	GMI,		NORMAL,		NORMAL,		INPUT),
+
+	DEFAULT_PINMUX(GMI_A16,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_A17,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_A18,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_A19,		GMI,		NORMAL,		NORMAL,		INPUT),
+
+	DEFAULT_PINMUX(GMI_AD0,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD1,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD2,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD3,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD4,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD5,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD6,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD7,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD8,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD9,		GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD10,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD11,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD12,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD13,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD14,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_AD15,	GMI,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(GMI_ADV_N,	GMI,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(GMI_CLK,		GMI,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(GMI_CS0_N,	GMI,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(GMI_OE_N,	GMI,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(GMI_RST_N,	GMI,		PULL_UP,	NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(GMI_WAIT,	GMI,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(GMI_WP_N,	GMI,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(GMI_WR_N,	GMI,		NORMAL,		NORMAL,		OUTPUT),
+
+	/* DISPLAY pinmux */
+	DEFAULT_PINMUX(LCD_D0,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D1,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D2,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D3,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D4,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D5,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D6,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D7,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D8,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D9,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D10,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D11,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D12,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D13,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D14,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D15,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D16,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D17,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D18,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D19,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D20,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D21,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D22,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_D23,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_DE,		DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_HSYNC,	DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_PCLK,	DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_VSYNC,	DISPLAYA,	NORMAL,		NORMAL,		OUTPUT),
+
+	/* PCIE */
+	DEFAULT_PINMUX(PEX_L0_CLKREQ_N,	PCIE,   	NORMAL,	    	NORMAL,		INPUT),
+	DEFAULT_PINMUX(PEX_L1_RST_N,	PCIE,		PULL_UP,	NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(PEX_L1_CLKREQ_N,	PCIE,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(PEX_L0_RST_N,	PCIE,		PULL_UP,	NORMAL,		OUTPUT),
+
+	VI_PINMUX(VI_D2,		VI,		NORMAL,		NORMAL,	  	INPUT, 	DISABLE,	DISABLE),
+	VI_PINMUX(VI_D3,		VI,		NORMAL,		NORMAL,         INPUT,	DISABLE,	DISABLE),
+	VI_PINMUX(VI_D4,		VI,		NORMAL,		NORMAL,	        INPUT,	DISABLE,	DISABLE),
+	VI_PINMUX(VI_D5,		VI,		NORMAL,		NORMAL,	        INPUT,	DISABLE,	DISABLE),
+	VI_PINMUX(VI_D6,		VI,		NORMAL,		NORMAL,	        INPUT,	DISABLE,	DISABLE),
+	VI_PINMUX(VI_D7,		VI,		NORMAL,		NORMAL,	        INPUT,	DISABLE,	DISABLE),
+	VI_PINMUX(VI_D8,		VI,		NORMAL,		NORMAL,	        INPUT,	DISABLE,	DISABLE),
+	VI_PINMUX(VI_D9,	    	VI,		NORMAL,		NORMAL,	        INPUT,	DISABLE,	DISABLE),
+	VI_PINMUX(VI_PCLK,	    	VI,		NORMAL,		NORMAL,	        INPUT,	DISABLE,	DISABLE),
+	VI_PINMUX(VI_HSYNC,	    	VI,		NORMAL,		NORMAL,	        INPUT,	DISABLE,	DISABLE),
+	VI_PINMUX(VI_VSYNC,	    	VI,		NORMAL,		NORMAL,	        INPUT,	DISABLE,	DISABLE),
+
+	/* pin config for gpios */
+	DEFAULT_PINMUX(PEX_L2_CLKREQ_N,	RSVD2,		PULL_UP,	NORMAL,	        INPUT),
+	DEFAULT_PINMUX(PEX_L1_PRSNT_N,	RSVD2,		PULL_UP,        NORMAL,		INPUT),
+	DEFAULT_PINMUX(LCD_CS1_N,	RSVD2,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(LCD_DC0,		RSVD1,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(LCD_DC1,		RSVD1,		PULL_UP,	NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(VI_D0,		RSVD1,		NORMAL,		NORMAL,		INPUT),
+	DEFAULT_PINMUX(ULPI_NXT,	RSVD,		NORMAL,		NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(ULPI_STP,	RSVD,		PULL_DOWN,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(CRT_VSYNC,	RSVD1,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(CRT_HSYNC,	RSVD1,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(LCD_PWR1,	RSVD1,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(LCD_PWR2,	RSVD,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(PEX_L0_PRSNT_N,	RSVD2,   	PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(GPIO_PV2,	RSVD1,	    	PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT7,	RSVD,    	PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(CLK_32K_OUT,	RSVD1,	    	PULL_DOWN, 	NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(CLK3_REQ,	RSVD1,	    	PULL_DOWN, 	NORMAL,		INPUT),
+	DEFAULT_PINMUX(GPIO_PV0,	RSVD,	    	PULL_DOWN, 	NORMAL,		INPUT),
+	DEFAULT_PINMUX(GPIO_PV1,	RSVD,	    	PULL_DOWN, 	NORMAL,		INPUT),
+	DEFAULT_PINMUX(LCD_M1,	    	RSVD1,		PULL_DOWN,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(VI_MCLK,	    	VI,		PULL_UP, 	NORMAL,		INPUT),
+	DEFAULT_PINMUX(LCD_WR_N,	RSVD,		PULL_DOWN,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(PEX_L2_PRSNT_N,	RSVD2,		PULL_DOWN,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(PEX_L2_RST_N,	RSVD2,		PULL_DOWN,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(PEX_WAKE_N,	RSVD2,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(HDMI_INT,	RSVD,		PULL_DOWN,	NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(KB_ROW1,		RSVD2,		PULL_DOWN,	NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(KB_ROW2,		RSVD2,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(KB_ROW3,		RSVD2,		PULL_UP,	NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(KB_ROW4,		RSVD3,		PULL_UP,	NORMAL,		INPUT),
+	DEFAULT_PINMUX(VI_D10,		RSVD1,		PULL_DOWN,	NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(VI_D11,		RSVD1,		PULL_UP,	NORMAL,		OUTPUT),
+	DEFAULT_PINMUX(LCD_PWR0,	DISPLAYA,	PULL_DOWN,	NORMAL,		INPUT),
+
+	/*
+	 * unused pins: tristate them all.
+	 */
+	DEFAULT_PINMUX(SPI2_CS0_N,	GMI,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SPI2_SCK,	GMI,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SPI2_MOSI,	GMI,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SPI2_MISO,	GMI,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU2,	GMI,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU3,	GMI,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU4,	GMI,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU5,	GMI,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PU6,	GMI,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(CLK1_REQ,	RSVD2,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT4,	SDMMC3,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SDMMC3_DAT5,	SDMMC3,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SPI2_CS1_N,	SPI2,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SPDIF_IN,	SPDIF,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SPDIF_OUT,	SAFE,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SPI1_CS0_N,	SPI1,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SPI1_MISO,	SPI1,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SPI1_MOSI,	SPI1,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(SPI1_SCK,	SPI1,		NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(CAM_MCLK,	POPSDMMC4,	NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PCC1,	POPSDMMC4,	NORMAL,		TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PCC2,	POPSDMMC4,	PULL_UP,	TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PBB0,	POPSDMMC4,	PULL_UP,	TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PBB3,	POPSDMMC4,	PULL_UP,	TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PBB4,	POPSDMMC4,	PULL_UP,	TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PBB5,	POPSDMMC4,	PULL_UP,	TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PBB6,	POPSDMMC4,	PULL_UP,	TRISTATE,	OUTPUT),
+	DEFAULT_PINMUX(GPIO_PBB7,	POPSDMMC4,	PULL_UP,	TRISTATE,	OUTPUT),
+
+};
+
+int __init e1853_pinmux_init(void)
+{
+	tegra_pinmux_config_table(e1853_pinmux_common,
+					ARRAY_SIZE(e1853_pinmux_common));
+	tegra_drive_pinmux_config_table(e1853_drive_pinmux,
+			ARRAY_SIZE(e1853_drive_pinmux));
+	return 0;
+}
+
+static struct gpio e1853_sku8_gpios[] = {
+	{TEGRA_GPIO_PV0,	GPIOF_IN,    		"v0"},
+	{TEGRA_GPIO_PV1,	GPIOF_IN,    		"v1"},
+	{TEGRA_GPIO_PY2,	GPIOF_OUT_INIT_HIGH,    "y2"},
+	{TEGRA_GPIO_PY3,	GPIOF_IN,		"y3"},
+	{TEGRA_GPIO_PV6,	GPIOF_IN,		"v6"},
+	{TEGRA_GPIO_PV7,	GPIOF_IN,		"v7"},
+	{TEGRA_GPIO_PW0,	GPIOF_IN,		"w0"},
+	{TEGRA_GPIO_PD2,	GPIOF_OUT_INIT_HIGH,	"d2"},
+	{TEGRA_GPIO_PW1,	GPIOF_IN,		"w1"},
+	{TEGRA_GPIO_PB2,	GPIOF_IN,		"b2"},
+	{TEGRA_GPIO_PC1,	GPIOF_IN,		"c1"},
+	{TEGRA_GPIO_PC6,	GPIOF_IN,		"c6"},
+	{TEGRA_GPIO_PZ3,	GPIOF_IN,		"z3"},
+	{TEGRA_GPIO_PDD0,	GPIOF_IN,		"dd0"},
+	{TEGRA_GPIO_PDD4,	GPIOF_IN,		"dd4"},
+	{TEGRA_GPIO_PCC7,	GPIOF_IN, 		"cc7"},
+	{TEGRA_GPIO_PDD7,	GPIOF_IN,		"dd7"},
+	{TEGRA_GPIO_PCC6,	GPIOF_IN,		"cc6"},
+	{TEGRA_GPIO_PDD3,	GPIOF_IN,		"dd3"},
+	{TEGRA_GPIO_PV2, 	GPIOF_IN,		"v2"},
+	{TEGRA_GPIO_PA0,	GPIOF_OUT_INIT_LOW,	"a0"},
+	{TEGRA_GPIO_PR1,	GPIOF_OUT_INIT_LOW,	"r1"},
+	{TEGRA_GPIO_PR2,	GPIOF_IN,		"r2"},
+	{TEGRA_GPIO_PR3, 	GPIOF_IN,		"r3"},
+	{TEGRA_GPIO_PR4, 	GPIOF_IN,		"r4"},
+	{TEGRA_GPIO_PEE1,	GPIOF_IN,		"ee1"},
+	{TEGRA_GPIO_PT2, 	GPIOF_OUT_INIT_LOW,	"t2"},
+	{TEGRA_GPIO_PT3, 	GPIOF_OUT_INIT_HIGH,	"t3"},
+	{TEGRA_GPIO_PT1, 	GPIOF_IN,    		"t1"},
+};
+int __init e1853_gpio_init(void)
+{
+	int i, pin_count = 0;
+	struct gpio *gpios_info = NULL;
+	gpios_info = e1853_sku8_gpios;
+	pin_count = ARRAY_SIZE(e1853_sku8_gpios);
+
+	gpio_request_array(gpios_info, pin_count);
+	for (i = 0; i < pin_count; i++) {
+		tegra_gpio_enable(gpios_info[i].gpio);
+		gpio_export(gpios_info[i].gpio, true);
+	}
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-e1853-sdhci.c b/arch/arm/mach-tegra/board-e1853-sdhci.c
new file mode 100644
index 000000000000..5446bb46df15
--- /dev/null
+++ b/arch/arm/mach-tegra/board-e1853-sdhci.c
@@ -0,0 +1,83 @@
+/*
+ * arch/arm/mach-tegra/board-e1853-sdhci.c
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/resource.h>
+#include <linux/platform_device.h>
+#include <linux/wlan_plat.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mmc/host.h>
+
+#include <asm/mach-types.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/sdhci.h>
+
+#include "gpio-names.h"
+#include "board.h"
+#include "board-e1853.h"
+#include "devices.h"
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data1 = {
+	.cd_gpio = -1,
+	.wp_gpio = -1,
+	.power_gpio = -1,
+	.is_8bit = false,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
+	.cd_gpio = -1,
+	.wp_gpio = -1,
+	.power_gpio = -1,
+	.is_8bit = 1,
+	.mmc_data = {
+		.built_in = 1,
+	}
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
+	.cd_gpio = TEGRA_GPIO_PN6,
+	.wp_gpio = TEGRA_GPIO_PD4,
+	.power_gpio = TEGRA_GPIO_PN7,
+	.is_8bit = false,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data4 = {
+	.cd_gpio = -1,
+	.wp_gpio = -1,
+	.power_gpio = -1,
+	.is_8bit = true,
+};
+
+int __init e1853_sdhci_init(void)
+{
+	tegra_sdhci_device1.dev.platform_data = &tegra_sdhci_platform_data1;
+	tegra_sdhci_device2.dev.platform_data = &tegra_sdhci_platform_data2;
+	tegra_sdhci_device3.dev.platform_data = &tegra_sdhci_platform_data3;
+	tegra_sdhci_device4.dev.platform_data = &tegra_sdhci_platform_data4;
+
+	platform_device_register(&tegra_sdhci_device1);
+	platform_device_register(&tegra_sdhci_device2);
+	platform_device_register(&tegra_sdhci_device3);
+	platform_device_register(&tegra_sdhci_device4);
+
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-e1853.c b/arch/arm/mach-tegra/board-e1853.c
new file mode 100644
index 000000000000..9379ec3b3f18
--- /dev/null
+++ b/arch/arm/mach-tegra/board-e1853.c
@@ -0,0 +1,391 @@
+/*
+ * arch/arm/mach-tegra/board-e1853.c
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/i2c/panjit_ts.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/i2c-tegra.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/platform_data/tegra_usb.h>
+#include <linux/platform_data/tegra_nor.h>
+#include <linux/spi/spi.h>
+#include <linux/mtd/partitions.h>
+#include <mach/clk.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/iomap.h>
+#include <mach/io.h>
+#include <mach/pci.h>
+#include <mach/audio.h>
+#include <mach/tegra_e1853_pdata.h>
+#include <asm/mach/flash.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/usb_phy.h>
+#include <sound/wm8903.h>
+#include <mach/tsensor.h>
+#include "board.h"
+#include "clock.h"
+#include "board-e1853.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "fuse.h"
+
+static __initdata struct tegra_clk_init_table e1853_clk_init_table[] = {
+	/* name		parent		rate		enabled */
+	{ "pll_m",		NULL,		0,		true},
+	{ "hda",		"pll_p",	108000000,	false},
+	{ "hda2codec_2x",	"pll_p",	48000000,	false},
+	{ "pwm",		"clk_32k",	32768,		false},
+	{ "blink",		"clk_32k",	32768,		true},
+	{ "pll_a",		NULL,		552960000,	false},
+	/* audio cif clock should be faster than i2s */
+	{ "pll_a_out0",		NULL,		24576000,	false},
+	{ "d_audio",		"pll_a_out0",	24576000,	false},
+	{ "nor",		"pll_p",	86500000,	true},
+	{ "uarta",		"pll_p",	480000000,	true},
+	{ "uartb",		"pll_p",	480000000,	true},
+	{ "uartc",		"pll_p",	480000000,	true},
+	{ "uartd",		"pll_p",	480000000,	true},
+	{ "sdmmc2",		"pll_p",	52000000,	true},
+	{ "sbc2",		"pll_m",	100000000,	true},
+	{ "sbc3",		"pll_m",	100000000,	true},
+	{ "sbc4",		"pll_m",	100000000,	true},
+	{ "sbc5",		"pll_m",	100000000,	true},
+	{ "sbc6",		"pll_m",	100000000,	true},
+	{ "cpu_g",		"cclk_g",	900000000,	true},
+	{ "i2s0",		"pll_a_out0",	24576000,	false},
+	{ "i2s1",		"pll_a_out0",	24576000,	false},
+	{ "i2s2",		"pll_a_out0",	24576000,	false},
+	{ "i2s3",		"pll_a_out0",	24576000,	false},
+	{ "i2s4",		"pll_a_out0",	24576000,	false},
+	{ "audio0",		"i2s0_sync",	12288000,	false},
+	{ "audio1",		"i2s1_sync",	12288000,	false},
+	{ "audio2",		"i2s2_sync",	12288000,	false},
+	{ "audio3",		"i2s3_sync",	12288000,	false},
+	{ "audio4",		"i2s4_sync",	12288000,	false},
+	{ "apbif",		"clk_m",	12000000,	false},
+	{ "dam0",		"clk_m",	12000000,	true},
+	{ "dam1",		"clk_m",	12000000,	true},
+	{ "dam2",		"clk_m",	12000000,	true},
+	{ "vi",			"pll_p",	470000000,	false},
+	{ "vi_sensor",		"pll_p",	150000000,	false},
+	{ "vde",		"pll_c",	484000000,	true},
+	{ "host1x",		"pll_c",	242000000,	true},
+	{ "mpe",		"pll_c",	484000000,	true},
+	{ "se",			"pll_m",	625000000,	true},
+	{ "i2c1",		"pll_p",	3200000,	true},
+	{ "i2c2",		"pll_p",	3200000,	true},
+	{ "i2c3",		"pll_p",	3200000,	true},
+	{ "i2c4",		"pll_p",	3200000,	true},
+	{ "i2c5",		"pll_p",	3200000,	true},
+	{ "sdmmc2",		"pll_p",	104000000,	false},
+	{"wake.sclk",		NULL,		334000000,	true },
+	{ NULL,			NULL,		0,		0},
+};
+
+static struct tegra_i2c_platform_data e1853_i2c1_platform_data = {
+	.adapter_nr	= 0,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 100000, 0 },
+};
+
+static struct tegra_i2c_platform_data e1853_i2c2_platform_data = {
+	.adapter_nr	= 1,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 100000, 0 },
+	.is_clkon_always = true,
+};
+
+static struct tegra_i2c_platform_data e1853_i2c4_platform_data = {
+	.adapter_nr	= 3,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 100000, 0 },
+};
+
+static struct tegra_i2c_platform_data e1853_i2c5_platform_data = {
+	.adapter_nr	= 4,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 100000, 0 },
+};
+
+static struct tegra_pci_platform_data e1853_pci_platform_data = {
+	.port_status[0] = 1,
+	.port_status[1] = 1,
+	.port_status[2] = 1,
+	.use_dock_detect = 0,
+	.gpio 		= 0,
+};
+
+static void e1853_pcie_init(void)
+{
+	tegra_pci_device.dev.platform_data = &e1853_pci_platform_data;
+	platform_device_register(&tegra_pci_device);
+}
+
+static void e1853_i2c_init(void)
+{
+	tegra_i2c_device1.dev.platform_data = &e1853_i2c1_platform_data;
+	tegra_i2c_device2.dev.platform_data = &e1853_i2c2_platform_data;
+	tegra_i2c_device4.dev.platform_data = &e1853_i2c4_platform_data;
+	tegra_i2c_device5.dev.platform_data = &e1853_i2c5_platform_data;
+
+	platform_device_register(&tegra_i2c_device5);
+	platform_device_register(&tegra_i2c_device4);
+	platform_device_register(&tegra_i2c_device2);
+	platform_device_register(&tegra_i2c_device1);
+}
+
+static struct platform_device *e1853_uart_devices[] __initdata = {
+	&tegra_uarta_device,
+	&tegra_uartb_device,
+	&tegra_uartc_device,
+	&tegra_uartd_device,
+};
+static struct clk *debug_uart_clk;
+
+static void __init uart_debug_init(void)
+{
+	/* UARTA is the debug port. */
+	pr_info("Selecting UARTA as the debug console\n");
+	e1853_uart_devices[0] = &debug_uarta_device;
+	debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
+}
+
+static void __init e1853_uart_init(void)
+{
+	/* Register low speed only if it is selected */
+	if (!is_tegra_debug_uartport_hs()) {
+		uart_debug_init();
+		/* Clock enable for the debug channel */
+		if (!IS_ERR_OR_NULL(debug_uart_clk)) {
+			pr_info("The debug console clock name is %s\n",
+						debug_uart_clk->name);
+			clk_enable(debug_uart_clk);
+			clk_set_rate(debug_uart_clk, 408000000);
+		} else {
+			pr_err("Not getting the clock %s for debug console\n",
+					debug_uart_clk->name);
+		}
+	}
+
+	platform_add_devices(e1853_uart_devices,
+				ARRAY_SIZE(e1853_uart_devices));
+}
+
+#if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV)
+static struct spi_board_info tegra_spi_devices[] __initdata = {
+	{
+		.modalias = "spidev",
+		.bus_num = 1,
+		.chip_select = 1,
+		.mode = SPI_MODE_0,
+		.max_speed_hz = 18000000,
+		.platform_data = NULL,
+		.irq = 0,
+	},
+	{
+		.modalias = "spidev",
+		.bus_num = 2,
+		.chip_select = 1,
+		.mode = SPI_MODE_0,
+		.max_speed_hz = 18000000,
+		.platform_data = NULL,
+		.irq = 0,
+	},
+	{
+		.modalias = "spidev",
+		.bus_num = 4,
+		.chip_select = 2,
+		.mode = SPI_MODE_0,
+		.max_speed_hz = 18000000,
+		.platform_data = NULL,
+		.irq = 0,
+	},
+};
+
+static void __init e1853_register_spidev(void)
+{
+	spi_register_board_info(tegra_spi_devices,
+			ARRAY_SIZE(tegra_spi_devices));
+}
+#else
+#define e1853_register_spidev() do {} while (0)
+#endif
+
+
+static void e1853_spi_init(void)
+{
+	tegra_spi_device3.name = "spi_slave_tegra";
+	platform_device_register(&tegra_spi_device2);
+	platform_device_register(&tegra_spi_device3);
+	platform_device_register(&tegra_spi_device5);
+	e1853_register_spidev();
+}
+
+static struct platform_device tegra_camera = {
+	.name = "tegra_camera",
+	.id = -1,
+};
+
+static struct platform_device *e1853_devices[] __initdata = {
+#if defined(CONFIG_TEGRA_IOVMM_SMMU)
+	&tegra_smmu_device,
+#endif
+#if defined(CONFIG_TEGRA_AVP)
+	&tegra_avp_device,
+#endif
+	&tegra_camera,
+	&tegra_wdt0_device
+};
+
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+	.port_otg = false,
+	.has_hostpc = true,
+	.phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+	.op_mode = TEGRA_USB_OPMODE_HOST,
+	.u_data.host = {
+		.vbus_gpio = -1,
+		.vbus_reg = NULL,
+		.hot_plug = false,
+		.remote_wakeup_supported = true,
+		.power_off_on_suspend = true,
+	},
+	.u_cfg.utmi = {
+		.hssync_start_delay = 0,
+		.idle_wait_delay = 17,
+		.elastic_limit = 16,
+		.term_range_adj = 6,
+		.xcvr_setup = 63,
+		.xcvr_setup_offset = 6,
+		.xcvr_use_fuses = 1,
+		.xcvr_lsfslew = 2,
+		.xcvr_lsrslew = 2,
+		.xcvr_use_lsb = 1,
+	},
+};
+
+static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
+	.port_otg = false,
+	.has_hostpc = true,
+	.phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+	.op_mode = TEGRA_USB_OPMODE_HOST,
+	.u_data.host = {
+		.vbus_gpio = -1,
+		.vbus_reg = NULL,
+		.hot_plug = false,
+		.remote_wakeup_supported = true,
+		.power_off_on_suspend = true,
+	},
+	.u_cfg.utmi = {
+		.hssync_start_delay = 0,
+		.idle_wait_delay = 17,
+		.elastic_limit = 16,
+		.term_range_adj = 6,
+		.xcvr_setup = 63,
+		.xcvr_setup_offset = 6,
+		.xcvr_use_fuses = 1,
+		.xcvr_lsfslew = 2,
+		.xcvr_lsrslew = 2,
+		.xcvr_use_lsb = 1,
+	},
+};
+
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+	.port_otg = false,
+	.has_hostpc = true,
+	.phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+	.op_mode = TEGRA_USB_OPMODE_HOST,
+	.u_data.host = {
+		.vbus_gpio = -1,
+		.vbus_reg = NULL,
+		.hot_plug = false,
+		.remote_wakeup_supported = true,
+		.power_off_on_suspend = true,
+	},
+	.u_cfg.utmi = {
+		.hssync_start_delay = 0,
+		.idle_wait_delay = 17,
+		.elastic_limit = 16,
+		.term_range_adj = 6,
+		.xcvr_setup = 63,
+		.xcvr_setup_offset = 6,
+		.xcvr_use_fuses = 1,
+		.xcvr_lsfslew = 2,
+		.xcvr_lsrslew = 2,
+		.xcvr_use_lsb = 1,
+	},
+};
+
+static void e1853_usb_init(void)
+{
+	tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata;
+	platform_device_register(&tegra_ehci1_device);
+
+	tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
+	platform_device_register(&tegra_ehci2_device);
+
+	tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
+	platform_device_register(&tegra_ehci3_device);
+}
+
+static void __init tegra_e1853_init(void)
+{
+	tegra_init_board_info();
+	tegra_clk_init_from_table(e1853_clk_init_table);
+	e1853_pinmux_init();
+	e1853_i2c_init();
+	e1853_gpio_init();
+	e1853_uart_init();
+	e1853_usb_init();
+	e1853_sdhci_init();
+	e1853_spi_init();
+	platform_add_devices(e1853_devices, ARRAY_SIZE(e1853_devices));
+	e1853_panel_init();
+	e1853_pcie_init();
+}
+
+static void __init tegra_e1853_reserve(void)
+{
+#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
+	tegra_reserve(0, SZ_8M, 0);
+#else
+	tegra_reserve(SZ_128M, SZ_8M, 0);
+#endif
+}
+
+MACHINE_START(E1853, "e1853")
+	.boot_params    = 0x80000100,
+	.init_irq       = tegra_init_irq,
+	.init_early     = tegra_init_early,
+	.init_machine   = tegra_e1853_init,
+	.map_io         = tegra_map_common_io,
+	.reserve        = tegra_e1853_reserve,
+	.timer          = &tegra_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-e1853.h b/arch/arm/mach-tegra/board-e1853.h
new file mode 100644
index 000000000000..58b8ab8725af
--- /dev/null
+++ b/arch/arm/mach-tegra/board-e1853.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-tegra/e1853/board-e1853.h
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _MACH_TEGRA_BOARD_E1853_H
+#define _MACH_TEGRA_BOARD_E1853_H
+
+int e1853_sdhci_init(void);
+int e1853_pinmux_init(void);
+int e1853_panel_init(void);
+int e1853_gpio_init(void);
+int e1853_pins_state_init(void);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/tegra_e1853_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_e1853_pdata.h
new file mode 100644
index 000000000000..633f04855e6e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_e1853_pdata.h
@@ -0,0 +1,55 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_e1853_pdata.h
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef __MACH_TEGRA_E1853_PDATA_H
+#define __MACH_TEGRA_E1853_PDATA_H
+
+#define NUM_AUDIO_CONTROLLERS 4
+
+/* data format supported */
+enum i2s_data_format {
+	format_i2s = 0x1,
+	format_dsp = 0x2,
+	format_rjm = 0x4,
+	format_ljm = 0x8,
+	format_tdm = 0x10
+};
+
+struct codec_info_s {
+	/* Name of the Codec Dai on the system */
+	char *codec_dai_name;
+	/* Name of the I2S controller dai its connected to */
+	char *cpu_dai_name;
+	char *codec_name;	/* Name of the Codec Driver */
+	char *name;			/* Name of the Codec-Dai-Link */
+	char *pcm_driver;	/* Name of the PCM driver */
+	enum i2s_data_format i2s_format;
+	int master;			/* Codec is Master or Slave */
+	/* TDM format setttings */
+	int num_slots;		/* Number of TDM slots */
+	int slot_width;		/* Width of each slot */
+	int rx_mask;		/* Number of Rx Enabled slots */
+	int tx_mask;		/* Number of Tx Enabled slots */
+
+};
+
+struct tegra_e1853_platform_data {
+	struct codec_info_s codec_info[NUM_AUDIO_CONTROLLERS];
+};
+#endif