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authorScott Williams <scwilliams@nvidia.com>2011-08-10 14:18:37 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:47:04 -0800
commit48e1e48251c6be3f9610ffe33dec9a684f2cf9f0 (patch)
tree48bf6dd835a045a75b3550e42d3f7da1e6d58045 /arch/arm/mach-tegra
parent607d5ec8bb46f95473533f611da1ffc97907d16e (diff)
ARM: tegra: timer: Save TWD counter instead of load register
In tegra_twd_suspend(), save the remaining count rather than the initial count of the timer. Also catch invalid TWD configurations during suspend/restore (e.g., enabled with a zero count). BUG 862605 Change-Id: I05bf9e37f922a2b0a48cff23f1aa94ec8e8e039e Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R6c7e5ae1220faee4564cd751fa6c94f7404ddc27
Diffstat (limited to 'arch/arm/mach-tegra')
-rw-r--r--arch/arm/mach-tegra/timer.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index c17d8e8ecca4..aa99b2f41a93 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -206,12 +206,19 @@ static struct syscore_ops tegra_timer_syscore_ops = {
void tegra_twd_suspend(struct tegra_twd_context *context)
{
context->twd_ctrl = readl(twd_base + TWD_TIMER_CONTROL);
- context->twd_load = readl(twd_base + TWD_TIMER_LOAD);
+ context->twd_load = readl(twd_base + TWD_TIMER_COUNTER);
+ if ((context->twd_load == 0) && (context->twd_ctrl &
+ (TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE))) {
+ WARN("%s: TWD enabled but counter was 0\n", __func__);
+ context->twd_load = 1;
+ }
__raw_writel(0, twd_base + TWD_TIMER_CONTROL);
}
void tegra_twd_resume(struct tegra_twd_context *context)
{
+ BUG_ON((context->twd_load == 0) && (context->twd_ctrl &
+ (TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE)));
writel(context->twd_load, twd_base + TWD_TIMER_LOAD);
writel(context->twd_ctrl, twd_base + TWD_TIMER_CONTROL);
}