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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2019-03-28 11:16:26 +0100
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2019-03-28 11:16:26 +0100
commit6f01eb5bf8e8110ab5f3a8e7b0f3abf19a205e4b (patch)
tree4b3147335ed97e4b487fd84bcb7a959a38d9656e /arch/arm/mm/cache-v7.S
parent8f234193b8cc35c44614e4a4b05f2d920ff562e4 (diff)
parent6b50202a4d53bf527c640467bcff68b50a5e38a2 (diff)
Merge tag 'v4.4.177' into toradex_vf_4.4-nextColibri-VF_LXDE-Image_2.8b6.183-20190331
This is the 4.4.177 stable release
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
-rw-r--r--arch/arm/mm/cache-v7.S8
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index a134d8a13d00..11d699af30ed 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -359,14 +359,16 @@ v7_dma_inv_range:
ALT_UP(W(nop))
#endif
mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
+ addne r0, r0, r2
tst r1, r3
bic r1, r1, r3
mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
-1:
- mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line
- add r0, r0, r2
cmp r0, r1
+1:
+ mcrlo p15, 0, r0, c7, c6, 1 @ invalidate D / U line
+ addlo r0, r0, r2
+ cmplo r0, r1
blo 1b
dsb st
ret lr