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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-03-28 14:32:06 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-03-28 14:32:06 +0100 |
| commit | 32aca03c2ce868d3412da0bb6ce6798c7bea357e (patch) | |
| tree | 01630dc4a6935df99bf7d11d34ff8d384fed86e2 /arch/arm/mm/cache-v7m.S | |
| parent | cfbbc7703fff59c67761c93a8b1de29a79f9841c (diff) | |
| parent | 60771fc402877163d07569addadcf18b86acb455 (diff) | |
Merge tag 'v4.9.166' into 4.9-2.3.x-imx
This is the 4.9.166 stable release
Diffstat (limited to 'arch/arm/mm/cache-v7m.S')
| -rw-r--r-- | arch/arm/mm/cache-v7m.S | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-v7m.S b/arch/arm/mm/cache-v7m.S index 816a7e44e6f1..d29927740a19 100644 --- a/arch/arm/mm/cache-v7m.S +++ b/arch/arm/mm/cache-v7m.S @@ -73,9 +73,11 @@ /* * dcimvac: Invalidate data cache line by MVA to PoC */ -.macro dcimvac, rt, tmp - v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC +.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo +.macro dcimvac\c, rt, tmp + v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC, \c .endm +.endr /* * dccmvau: Clean data cache line by MVA to PoU @@ -369,14 +371,16 @@ v7m_dma_inv_range: tst r0, r3 bic r0, r0, r3 dccimvacne r0, r3 + addne r0, r0, r2 subne r3, r2, #1 @ restore r3, corrupted by v7m's dccimvac tst r1, r3 bic r1, r1, r3 dccimvacne r1, r3 -1: - dcimvac r0, r3 - add r0, r0, r2 cmp r0, r1 +1: + dcimvaclo r0, r3 + addlo r0, r0, r2 + cmplo r0, r1 blo 1b dsb st ret lr |