diff options
author | Sang-Hun Lee <sanlee@nvidia.com> | 2012-04-16 10:55:04 -0700 |
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committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-04-19 07:41:37 -0700 |
commit | d37014951a2e983935311582d72ad1fd48db6f5c (patch) | |
tree | eb7efed348af4a3fdcfe8c1e65f479f585258636 /arch/arm/mm/proc-arm920.S | |
parent | 1402e0b6a6069de57972e63821fd60e9e9fcc170 (diff) |
Revert "ARM: pm: only use preallocated page table during resume"
This reverts commit 46d9f14943770c24603ef7cdfd8eb2dbcd3c1248.
Bug 967887
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Change-Id: Iee732d8137043240902201d7783d2c3fede98fbe
Reviewed-on: http://git-master/r/96794
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'arch/arm/mm/proc-arm920.S')
-rw-r--r-- | arch/arm/mm/proc-arm920.S | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 88fb3d9e0640..035d57bf1b7a 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -379,26 +379,27 @@ ENTRY(cpu_arm920_set_pte_ext) /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ .globl cpu_arm920_suspend_size -.equ cpu_arm920_suspend_size, 4 * 3 +.equ cpu_arm920_suspend_size, 4 * 4 #ifdef CONFIG_PM_SLEEP ENTRY(cpu_arm920_do_suspend) - stmfd sp!, {r4 - r6, lr} + stmfd sp!, {r4 - r7, lr} mrc p15, 0, r4, c13, c0, 0 @ PID mrc p15, 0, r5, c3, c0, 0 @ Domain ID - mrc p15, 0, r6, c1, c0, 0 @ Control register - stmia r0, {r4 - r6} - ldmfd sp!, {r4 - r6, pc} + mrc p15, 0, r6, c2, c0, 0 @ TTB address + mrc p15, 0, r7, c1, c0, 0 @ Control register + stmia r0, {r4 - r7} + ldmfd sp!, {r4 - r7, pc} ENDPROC(cpu_arm920_do_suspend) ENTRY(cpu_arm920_do_resume) mov ip, #0 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches - ldmia r0, {r4 - r6} + ldmia r0, {r4 - r7} mcr p15, 0, r4, c13, c0, 0 @ PID mcr p15, 0, r5, c3, c0, 0 @ Domain ID - mcr p15, 0, r1, c2, c0, 0 @ TTB address - mov r0, r6 @ control register + mcr p15, 0, r6, c2, c0, 0 @ TTB address + mov r0, r7 @ control register b cpu_resume_mmu ENDPROC(cpu_arm920_do_resume) #endif |