diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-08-28 10:30:34 +0100 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-04-05 17:52:29 -0700 |
| commit | 16e0bb8c46656b1d902d422e0065c746af161a1c (patch) | |
| tree | 5ad5297077f6ef6710b773e65af318343ec3ca18 /arch/arm/mm/proc-v7.S | |
| parent | 5682179d980e1a70bcf37fd97a14e27a2ddde822 (diff) | |
ARM: pm: no need to save/restore context ID register
There is no need to save and restore the context ID register on ARMv6
and ARMv7 with a temporary page table as we write the context ID
register when we switch back to the real page tables for the thread.
Moreover, the temporary page tables do not contain any non-global
mappings, so the context ID value should not be used. To be safe,
initialize the register to a reserved context ID value.
Change-Id: I7de05e736dde5bc1b8ab682a8660eaaba52104cf
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/85727
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index b29fa5c7a5ee..bd0f3a18ab41 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -263,9 +263,8 @@ ENTRY(cpu_v7_do_suspend) stmfd sp!, {r0, r3 - r10, lr} mrc p15, 0, r3, c15, c0, 1 @ diag mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID - mrc p15, 0, r5, c13, c0, 1 @ Context ID - mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID - stmia r0!, {r3 - r6} + mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID + stmia r0!, {r3 - r5} mrc p15, 0, r6, c3, c0, 0 @ Domain ID mrc p15, 0, r7, c2, c0, 1 @ TTB 1 mrc p15, 0, r8, c1, c0, 0 @ Control register @@ -357,13 +356,13 @@ ENTRY(cpu_v7_do_resume) mov ip, #0 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache - ldmia r0!, {r3 - r6} + mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID + ldmia r0!, {r3 - r5} #ifndef CONFIG_TRUSTED_FOUNDATIONS mcr p15, 0, r3, c15, c0, 1 @ diag #endif mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID - mcr p15, 0, r5, c13, c0, 1 @ Context ID - mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID + mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID ldmia r0!, {r6 - r10} mcr p15, 0, r6, c3, c0, 0 @ Domain ID ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) @@ -400,8 +399,8 @@ ENTRY(cpu_v7_do_resume) ldrne r4, [r0], #4 mcrne p14, 0, r4, c0, c0, 2 @ DBGDTRRXext - mrc p14, 0, r4, c0, c0, 0 @ read IDR - mov r3, r4, lsr #24 + mrc p14, 0, r6, c0, c0, 0 @ read IDR + mov r3, r6, lsr #24 and r3, r3, #0xf @ r3 has the number of brkpt rsb r3, r3, #0xf @@ -430,7 +429,7 @@ ENTRY(cpu_v7_do_resume) restore_brkpt c1 restore_brkpt c0 - mov r3, r4, lsr #28 @ r3 has the number of wpt + mov r3, r6, lsr #28 @ r3 has the number of wpt rsb r3, r3, #0xf /* r3 = (15 - #of wpt) ; |