diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2012-03-27 17:26:39 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-04-05 17:52:25 -0700 |
| commit | 46d9f14943770c24603ef7cdfd8eb2dbcd3c1248 (patch) | |
| tree | c8aa28791f49856d583e83831d2aab328e3e821f /arch/arm/mm/proc-v7.S | |
| parent | 55f0f45a45263ba26bd473f50f867d29dd836e46 (diff) | |
ARM: pm: only use preallocated page table during resume
Only use the preallocated page table during the resume, not while
suspending. This avoids the overhead of having to switch unnecessarily
to the resume page table in the suspend path.
Change-Id: Ib71c9b60b0ec39749aadc6f592549d213e6a852e
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/85725
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 51 |
1 files changed, 26 insertions, 25 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 96385a7fee81..b29fa5c7a5ee 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -260,19 +260,18 @@ ENDPROC(cpu_v7_set_pte_ext) .equ cpu_v7_suspend_size, (4 * 10) + cpu_v7_debug_suspend_size #ifdef CONFIG_PM_SLEEP ENTRY(cpu_v7_do_suspend) - stmfd sp!, {r0, r3 - r11, lr} + stmfd sp!, {r0, r3 - r10, lr} mrc p15, 0, r3, c15, c0, 1 @ diag mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID mrc p15, 0, r5, c13, c0, 1 @ Context ID mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID stmia r0!, {r3 - r6} mrc p15, 0, r6, c3, c0, 0 @ Domain ID - mrc p15, 0, r7, c2, c0, 0 @ TTB 0 - mrc p15, 0, r8, c2, c0, 1 @ TTB 1 - mrc p15, 0, r9, c1, c0, 0 @ Control register - mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register - mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control - stmia r0!, {r6 - r11} + mrc p15, 0, r7, c2, c0, 1 @ TTB 1 + mrc p15, 0, r8, c1, c0, 0 @ Control register + mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control + stmia r0!, {r6 - r10} #ifdef CONFIG_ARM_SAVE_DEBUG_CONTEXT /* Save CP14 debug controller context */ @@ -297,7 +296,7 @@ ENTRY(cpu_v7_do_suspend) mrc p14, 0, r8, c0, c0, 0 @ read IDR mov r3, r8, lsr #24 - and r3, r3, #0xf @ r3 has the number of brkpt + and r3, r3, #0xf @ r3 has the number of brkpt rsb r3, r3, #0xf /* r3 = (15 - #of brkpt) ; @@ -324,7 +323,7 @@ ENTRY(cpu_v7_do_suspend) save_brkpt c1 save_brkpt c0 - mov r3, r8, lsr #28 @ r3 has the number of wpt + mov r3, r8, lsr #28 @ r3 has the number of wpt rsb r3, r3, #0xf /* r3 = (15 - #of wpt) ; @@ -351,7 +350,7 @@ ENTRY(cpu_v7_do_suspend) save_wpt c1 save_wpt c0 #endif - ldmfd sp!, {r0, r3 - r11, pc} + ldmfd sp!, {r0, r3 - r10, pc} ENDPROC(cpu_v7_do_suspend) ENTRY(cpu_v7_do_resume) @@ -365,15 +364,17 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID mcr p15, 0, r5, c13, c0, 1 @ Context ID mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID - ldmia r0!, {r6 - r11} + ldmia r0!, {r6 - r10} mcr p15, 0, r6, c3, c0, 0 @ Domain ID - mcr p15, 0, r7, c2, c0, 0 @ TTB 0 - mcr p15, 0, r8, c2, c0, 1 @ TTB 1 + ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) + ALT_UP(orr r1, r1, #TTB_FLAGS_UP) + mcr p15, 0, r1, c2, c0, 0 @ TTB 0 + mcr p15, 0, r7, c2, c0, 1 @ TTB 1 mcr p15, 0, ip, c2, c0, 2 @ TTB control register mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register - teq r4, r10 @ Is it already set? - mcrne p15, 0, r10, c1, c0, 1 @ No, so write it - mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control + teq r4, r9 @ Is it already set? + mcrne p15, 0, r9, c1, c0, 1 @ No, so write it + mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control ldr r4, =PRRR @ PRRR ldr r5, =NMRR @ NMRR mcr p15, 0, r4, c10, c2, 0 @ write PRRR @@ -382,7 +383,6 @@ ENTRY(cpu_v7_do_resume) #ifdef CONFIG_ARM_SAVE_DEBUG_CONTEXT /* Restore CP14 debug controller context */ - ldmia r0!, {r2 - r5} mcr p14, 0, r3, c0, c6, 0 @ DBGWFAR mcr p14, 0, r4, c0, c7, 0 @ DBGVCR @@ -400,14 +400,15 @@ ENTRY(cpu_v7_do_resume) ldrne r4, [r0], #4 mcrne p14, 0, r4, c0, c0, 2 @ DBGDTRRXext - mrc p14, 0, r8, c0, c0, 0 @ read IDR - mov r3, r8, lsr #24 - and r3, r3, #0xf @ r3 has the number of brkpt + mrc p14, 0, r4, c0, c0, 0 @ read IDR + mov r3, r4, lsr #24 + and r3, r3, #0xf @ r3 has the number of brkpt rsb r3, r3, #0xf - /* r3 = (15 - #of wpt) ; - switch offset = r3*12 - 4 = (r3*3 - 1)<<2 - */ + /* + * r3 = (15 - # of wpt) ; + * switch offset = r3*12 - 4 = (r3*3 - 1)<<2 + */ add r3, r3, r3, lsl #1 sub r3, r3, #1 add pc, pc, r3, lsl #2 @@ -429,7 +430,7 @@ ENTRY(cpu_v7_do_resume) restore_brkpt c1 restore_brkpt c0 - mov r3, r8, lsr #28 @ r3 has the number of wpt + mov r3, r4, lsr #28 @ r3 has the number of wpt rsb r3, r3, #0xf /* r3 = (15 - #of wpt) ; @@ -462,7 +463,7 @@ start_restore_wpt: isb #endif dsb - mov r0, r9 @ control register + mov r0, r8 @ Control Register b cpu_resume_mmu ENDPROC(cpu_v7_do_resume) #endif |