diff options
| author | Antti P Miettinen <amiettinen@nvidia.com> | 2013-01-10 15:29:53 +0200 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:08:10 -0700 |
| commit | 339e075ff0c24b441b5e5893689e49f993a786bd (patch) | |
| tree | caad4f770b707cebcd871fe859a3a9de928ec406 /arch/arm/mm/proc-v7.S | |
| parent | f188ccb54717b31d6e8b764b86fcc79a0d91f7cf (diff) | |
ARM: mm: Save and restore event counters
Save and restore event counter selections and counter
values over power gating.
Change-Id: If9b467781e94cb08b8cf8a980fff00eb5af71250
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/192646
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 43 |
1 files changed, 29 insertions, 14 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 80a3ed696bb5..05c7e97b7e8d 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -132,7 +132,7 @@ ENDPROC(cpu_v7_dcache_clean_area) #endif .globl cpu_v7_suspend_size -.equ cpu_v7_suspend_size, (4 * 17) + cpu_v7_debug_suspend_size +.equ cpu_v7_suspend_size, (4 * 26) + cpu_v7_debug_suspend_size #ifdef CONFIG_ARM_CPU_SUSPEND ENTRY(cpu_v7_do_suspend) stmfd sp!, {r3 - r10, lr} @@ -141,15 +141,23 @@ ENTRY(cpu_v7_do_suspend) mrc p15, 0, r6, c15, c0, 1 @ diag stmia r0!, {r4 - r6} - mrc p15, 0, r4, c9, c14, 2 @ PMINTENCLR - mrc p15, 0, r5, c9, c14, 0 @ PMUSEREN - mrc p15, 0, r6, c9, c12, 5 @ PMSELR, event counter selection - mrc p15, 0, r7, c9, c13, 2 @ PMXEVCNTR, event counter - mrc p15, 0, r8, c9, c13, 1 @ PMXEVTYPER or PMCCFILTR + mrc p15, 0, r7, c9, c14, 2 @ PMINTENCLR + mrc p15, 0, r8, c9, c14, 0 @ PMUSEREN mrc p15, 0, r9, c9, c13, 0 @ PMCCNTR, cycle counter mrc p15, 0, r10, c9, c12, 0 @ PMCR, control register + bic r6, r10, #1 @ disable counters + mcr p15, 0, r6, c9, c12, 0 @ write PMCR mrc p15, 0, r11, c9, c12, 1 @ PMCNTENSET, counter enable set - stmia r0!, {r4 - r11} + stmia r0!, {r7 - r11} + mov r7, r10, lsr #11 @ PMCR/N (number of event counters) + and r7, r7, #0x1f @ bits 15:11, 5 bits + sub r7, r7, #1 @ start from last +1: mcr p15, 0, r7, c9, c12, 5 @ set PMSELR + mrc p15, 0, r8, c9, c13, 1 @ read PMXEVTYPER + mrc p15, 0, r9, c9, c13, 2 @ read PMXEVCNTR + stmia r0!, {r8 - r9} + subs r7, #1 + bpl 1b mrc p15, 0, r6, c3, c0, 0 @ Domain ID mrc p15, 0, r7, c2, c0, 1 @ TTB 1 @@ -260,15 +268,22 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r6, c15, c0, 1 @ diag #endif - ldmia r0!, {r4 - r11} - mcr p15, 0, r4, c9, c14, 2 @ PMINTENCLR - mcr p15, 0, r5, c9, c14, 0 @ PMUSEREN - mcr p15, 0, r6, c9, c12, 5 @ PMSELR, event counter selection - mcr p15, 0, r7, c9, c13, 2 @ PMXEVCNTR, event counter - mcr p15, 0, r8, c9, c13, 1 @ PMXEVTYPER or PMCCFILTR + ldmia r0!, {r7 - r11} + mcr p15, 0, r7, c9, c14, 2 @ PMINTENCLR + mcr p15, 0, r8, c9, c14, 0 @ PMUSEREN mcr p15, 0, r9, c9, c13, 0 @ PMCCNTR, cycle counter - mcr p15, 0, r10, c9, c12, 0 @ PMCR, control register mcr p15, 0, r11, c9, c12, 1 @ PMCNTENSET, counter enable set + @ restore PMCR later + mov r7, r10, lsr #11 @ PMCR/N (number of event counters) + and r7, r7, #0x1f @ bits 15:11, 5 bits + sub r7, r7, #1 @ start from last +1: mcr p15, 0, r7, c9, c12, 5 @ set PMSELR + ldmia r0!, {r8 - r9} + mcr p15, 0, r8, c9, c13, 1 @ write PMXEVTYPER + mcr p15, 0, r9, c9, c13, 2 @ write PMXEVCNTR + subs r7, #1 + bpl 1b + mcr p15, 0, r10, c9, c12, 0 @ PMCR, control register ldmia r0!, {r6 - r11} mcr p15, 0, r6, c3, c0, 0 @ Domain ID |