diff options
| author | Bo Yan <byan@nvidia.com> | 2012-12-28 11:35:52 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:49:02 -0700 |
| commit | 4bbf6f882c03343d72c1f437221fe87c6eebe06f (patch) | |
| tree | c910c489898239b9ae23a18bc06d4c16d4774e20 /arch/arm/mm/proc-v7.S | |
| parent | 9ca5f50011ccd5a368a539f06a259246ba51ee2d (diff) | |
ARM: tegra11x: start L2 clock before enabling SMP
Do an external device read to start L2 clock, then change
SMP bit in ACTLR. The ACTLR change needs to be done immediately
after the device read is done since there are only 256 clock cycles
maximum available before the L2 clock can be gated again.
bug 1208654
bug 1195192
Change-Id: Ide1c0476d629cbea07f585013ed3b7e79a67c86e
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/187521
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bobby Meeker <bmeeker@nvidia.com>
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index ca59770470b5..7c29db4ea0db 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -25,6 +25,8 @@ #include "proc-v7-2level.S" #endif +#define TEGRA_CLK_RESET_BOND_OUT 0x60006070 + ENTRY(cpu_v7_proc_init) mov pc, lr ENDPROC(cpu_v7_proc_init) @@ -277,6 +279,12 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r1, c2, c0, 0 @ TTB 0 mcr p15, 0, r7, c2, c0, 1 @ TTB 1 mcr p15, 0, r11, c2, c0, 2 @ TTB control register +#ifdef CONFIG_ARCH_TEGRA_11x_SOC + ldr r4, =TEGRA_CLK_RESET_BOND_OUT + ldr r4, [r4] + tst r4, #1 + bne . +#endif mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register teq r4, r9 @ Is it already set? mcrne p15, 0, r9, c1, c0, 1 @ No, so write it @@ -436,6 +444,19 @@ __v7_ca15mp_setup: mrc p15, 0, r0, c1, c0, 1 orr r0, #(1<<24) @ Enable NCSE in ACTLR mcr p15, 0, r0, c1, c0, 1 + + ldr r0, =TEGRA_CLK_RESET_BOND_OUT + ldr r0, [r0] + tst r0, #1 + bne . + + ALT_SMP(mrc p15, 0, r0, c1, c0, 1) + ALT_UP(mov r0, #(1 << 6)) @ fake it for UP + tst r0, #(1 << 6) @ SMP/nAMP mode enabled? + orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode + mcreq p15, 0, r0, c1, c0, 1 + + b __v7_setup #endif __v7_ca7mp_setup: mov r10, #0 |