diff options
| author | Clark Williams <williams@redhat.com> | 2012-02-03 15:10:42 -0600 |
|---|---|---|
| committer | Clark Williams <williams@redhat.com> | 2012-02-03 15:10:42 -0600 |
| commit | 77f57fb93d132875acead3581bcdc5d2fefbe7a0 (patch) | |
| tree | 5db5ccf5e1754248edc790e2f37f3a2b863f0ddb /arch/arm/mm/proc-v7.S | |
| parent | d28048db190097536aef2be5ee9a736bd7bb92eb (diff) | |
| parent | 69bade053d0f2ef0c8ee98af9f6699a55a8d8bb9 (diff) | |
Merge commit 'v3.2.3' into rt-3.2.3-rt10
Diffstat (limited to 'arch/arm/mm/proc-v7.S')
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index e70a73731eaa..40cc7aa1017d 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -271,10 +271,6 @@ ENDPROC(cpu_v7_do_resume) * Initialise TLB, Caches, and MMU state ready to switch the MMU * on. Return in r0 the new CP15 C1 control register setting. * - * We automatically detect if we have a Harvard cache, and use the - * Harvard cache control instructions insead of the unified cache - * control instructions. - * * This should be able to cover all ARMv7 cores. * * It is assumed that: @@ -373,9 +369,7 @@ __v7_setup: #endif 3: mov r10, #0 -#ifdef HARVARD_CACHE mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate -#endif dsb #ifdef CONFIG_MMU mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |