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| author | Arnd Bergmann <arnd@arndb.de> | 2019-01-30 17:57:26 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2019-01-30 17:57:55 +0100 |
| commit | 0b03e47d529df540f51b41a96478bb24b0eb51c9 (patch) | |
| tree | 15ab311d7324727ab65394c082f5afdc0678c9d4 /arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | |
| parent | 0f7be8f5bdf0d164fd1bc5d7dc76746469e1ccde (diff) | |
| parent | 55ec26d6a4241363fa94f15377ebd8f1116fbfd7 (diff) | |
Merge tag 'sunxi-dt64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Allwinner DT64 changes for 5.1
A few small improvements for the A64 this cycle:
- ARM PMU added
- Allwinner ARM architected timer workaround enabled
This works around timer value wrapping found in the Allwinner
implementation of the ARM architected timer.
* tag 'sunxi-dt64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: a64: Enable A64 timer workaround
arm64: dts: allwinner: a64: Fix a typo
arm64: dts: allwinner: a64: Add PMU node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 1583afd034ae..cca554c8353f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -142,6 +142,15 @@ clock-output-names = "ext-osc32k"; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -191,6 +200,7 @@ timer { compatible = "arm,armv8-timer"; + allwinner,erratum-unknown1; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 |