diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2018-07-30 13:31:19 +0100 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2018-08-27 15:42:52 +0800 |
| commit | 39defc813264ea87c837900af6f39964353d6b41 (patch) | |
| tree | 5bca4ac8b775212b700637b2679f2a4ddafe082e /arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | |
| parent | fcddd1f609ea39dc8377cc587d070e49d32940ff (diff) | |
arm64: dts: allwinner: a64: Add L2 cache nodes
Current kernels complain when booting on an A64 Soc:
....
[ 1.904297] cacheinfo: Unable to detect cache hierarchy for CPU 0
....
Not a real biggie on this flat topology, but also easy enough to fix.
Add the L2 cache node and let each CPU point to it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 925bf38fb536..b73f9287c3f0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -88,6 +88,7 @@ device_type = "cpu"; reg = <0>; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -95,6 +96,7 @@ device_type = "cpu"; reg = <1>; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -102,6 +104,7 @@ device_type = "cpu"; reg = <2>; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -109,6 +112,12 @@ device_type = "cpu"; reg = <3>; enable-method = "psci"; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; }; }; |