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authorRichard Zhu <hongxing.zhu@nxp.com>2020-01-17 15:19:56 +0800
committerRichard Zhu <hongxing.zhu@nxp.com>2020-02-25 15:50:35 +0800
commit73a14019d0d4ccf3d0acbd20e8a6f980ceb7035b (patch)
treef50d5704e6d091b192a94a04ae4a06530ce49344 /arch/arm64/boot/dts/freescale/Makefile
parent041b7a6f981bbf4785c83d747f71684b131f1ebd (diff)
MLK-23233-4 arm64: dts: refine pcie dts and add the pcieax2 and pciebx1 usecase
Different usecase maybe used by customer, add the PCIEA two lanes and PCIEB one lane usecase into fsl-imx8qm-pcieax2pciebx1.dts. Refine the PCIE dts nodes, add the requrired HSIO peripheral clocks for different consumers. PCIEB has one more PER clock, since the PCIEA CSR register would be configuired when PCIEB is initialized. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/Makefile')
-rw-r--r--arch/arm64/boot/dts/freescale/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 66918738ce76..c205e89bcab6 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \
fsl-imx8qm-mek-domu-dpu1-hdmi.dtb \
fsl-imx8qm-mek-root.dtb \
fsl-imx8qm-mek-inmate.dtb \
+ fsl-imx8qm-pcieax2pciebx1.dtb \
fsl-imx8qm-lpddr4-arm2-dp.dtb \
fsl-imx8qm-lpddr4-arm2-hdmi.dtb \
fsl-imx8qm-lpddr4-arm2-hdmi-in.dtb \