MLK-21823-2 arm64: dts: freescale: add i.MX8MN DT files

Add new SoC i.MX8MN's DT files and support it by default.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Ella Feng <ella.feng@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>

1 files changed, 1027 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi
new file mode 100644
index 000000000000..bc5e2905e982
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mn.dtsi
@@ -0,0 +1,1027 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8-ca53.dtsi"
+#include <dt-bindings/clock/imx8mn-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/pins-imx8mn.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	compatible = "fsl,imx8mn";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &fec1;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
+		i2c3 = &i2c4;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		spi0 = &ecspi1;
+		spi1 = &ecspi2;
+		spi2 = &ecspi3;
+	};
+
+	cpus {
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP: cpu-sleep {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010033>;
+				local-timer-stop;
+				entry-latency-us = <1000>;
+				exit-latency-us = <700>;
+				min-residency-us = <2700>;
+				wakeup-latency-us = <1500>;
+			};
+		};
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0 0x80000000>;
+	};
+
+	gic: interrupt-controller@38800000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+		clock-frequency = <8000000>;
+		arm,no-tick-in-suspend;
+	};
+
+	ddr_pmu0: ddr_pmu@3d800000 {
+		compatible = "fsl,imx8m-ddr-pmu", "fsl,imx8-ddr-pmu";
+		reg = <0x0 0x3d800000 0x0 0x400000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		osc_32k: clock@0 {
+			compatible = "fixed-clock";
+			reg = <0>;
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+			clock-output-names = "osc_32k";
+		};
+
+		osc_24m: clock@1 {
+			compatible = "fixed-clock";
+			reg = <1>;
+			#clock-cells = <0>;
+			clock-frequency = <24000000>;
+			clock-output-names = "osc_24m";
+		};
+
+		clk_ext1: clock@2 {
+			compatible = "fixed-clock";
+			reg = <3>;
+			#clock-cells = <0>;
+			clock-frequency = <133000000>;
+			clock-output-names = "clk_ext1";
+		};
+
+		clk_ext2: clock@3 {
+			compatible = "fixed-clock";
+			reg = <4>;
+			#clock-cells = <0>;
+			clock-frequency = <133000000>;
+			clock-output-names = "clk_ext2";
+		};
+
+		clk_ext3: clock@4 {
+			compatible = "fixed-clock";
+			reg = <5>;
+			#clock-cells = <0>;
+			clock-frequency = <133000000>;
+			clock-output-names = "clk_ext3";
+		};
+
+		clk_ext4: clock@5 {
+			compatible = "fixed-clock";
+			reg = <6>;
+			#clock-cells = <0>;
+			clock-frequency= <133000000>;
+			clock-output-names = "clk_ext4";
+		};
+	};
+
+	spba-bus@30000000 {
+		compatible = "fsl,spba-bus", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0x0 0x30000000 0x0 0x100000>;
+		ranges;
+
+		easrc: easrc@300C0000 {
+			compatible = "fsl,imx8mn-easrc";
+			reg = <0x0 0x300C0000 0x0 0x10000>;
+			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
+			clock-names = "mem";
+			dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
+			       <&sdma2 18 23 0> , <&sdma2 19 23 0>,
+			       <&sdma2 20 23 0> , <&sdma2 21 23 0>,
+			       <&sdma2 22 23 0> , <&sdma2 23 23 0>;
+			dma-names = "ctx0_rx", "ctx0_tx",
+				    "ctx1_rx", "ctx1_tx",
+				    "ctx2_rx", "ctx2_tx",
+				    "ctx3_rx", "ctx3_tx";
+			fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin";
+			fsl,asrc-rate  = <8000>;
+			fsl,asrc-width = <16>;
+			status = "disabled";
+		};
+
+		sai2: sai@30020000 {
+			compatible = "fsl,imx8mq-sai",
+				     "fsl,imx6sx-sai";
+			reg = <0x0 0x30020000 0x0 0x10000>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
+				<&clk IMX8MN_CLK_DUMMY>,
+				<&clk IMX8MN_CLK_SAI2_ROOT>,
+				<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
+			clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+			dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		sai3: sai@30030000 {
+			compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai";
+			reg = <0x0 0x30030000 0x0 0x10000>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
+				 <&clk IMX8MN_CLK_DUMMY>,
+				 <&clk IMX8MN_CLK_SAI3_ROOT>,
+				 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
+			clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+			dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		sai5: sai@30050000 {
+			compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai", "fsl,imx6sx-sai";
+			reg = <0x0 0x30050000 0x0 0x10000>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
+				 <&clk IMX8MN_CLK_DUMMY>,
+				 <&clk IMX8MN_CLK_SAI5_ROOT>,
+				 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
+			clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+			dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
+			dma-names = "rx", "tx";
+			fsl,shared-interrupt;
+			fsl,dataline = <0xf 0xf>;
+			status = "disabled";
+		};
+
+		sai6: sai@30060000 {
+			compatible = "fsl,imx8mq-sai",
+				     "fsl,imx6sx-sai";
+			reg = <0x0 0x30060000 0x0 0x10000>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
+				 <&clk IMX8MN_CLK_DUMMY>,
+				 <&clk IMX8MN_CLK_SAI6_ROOT>,
+				 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
+			clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+			dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		sai7: sai@300b0000 {
+			compatible = "fsl,imx8mq-sai",
+				     "fsl,imx6sx-sai";
+			reg = <0x0 0x300b0000 0x0 0x10000>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
+				 <&clk IMX8MN_CLK_DUMMY>,
+				 <&clk IMX8MN_CLK_SAI7_ROOT>,
+				 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
+			clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+			dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
+		micfil: micfil@30080000 {
+			compatible = "fsl,imx8mm-micfil";
+			reg = <0x0 0x30080000 0x0 0x10000>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MN_CLK_PDM_IPG>,
+				 <&clk IMX8MN_CLK_PDM_ROOT>,
+				 <&clk IMX8MN_AUDIO_PLL1_OUT>,
+				 <&clk IMX8MN_AUDIO_PLL2_OUT>,
+				 <&clk IMX8MN_CLK_EXT3>;
+			clock-names = "ipg_clk", "ipg_clk_app",
+				      "pll8k", "pll11k", "clkext3";
+			dmas = <&sdma2 24 26 0x80000000>;
+			dma-names = "rx";
+			status = "disabled";
+		};
+
+		spdif1: spdif@30090000 {
+			compatible = "fsl,imx8mm-spdif";
+			reg = <0x0 0x30090000 0x0 0x10000>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
+				 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
+				 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
+				 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
+				 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
+				 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
+				 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
+				 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
+				 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
+				 <&clk IMX8MN_CLK_DUMMY>; /* spba */
+			clock-names = "core", "rxtx0",
+				      "rxtx1", "rxtx2",
+				      "rxtx3", "rxtx4",
+				      "rxtx5", "rxtx6",
+				      "rxtx7", "spba";
+			dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+	};
+
+	gpio1: gpio@30200000 {
+		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x30200000 0x0 0x10000>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio2: gpio@30210000 {
+		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x30210000 0x0 0x10000>;
+		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio3: gpio@30220000 {
+		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x30220000 0x0 0x10000>;
+		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio4: gpio@30230000 {
+		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x30230000 0x0 0x10000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio5: gpio@30240000 {
+		compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x30240000 0x0 0x10000>;
+		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	tmu: tmu@0x30260000 {
+		compatible = "fsl,imx8mm-tmu";
+		reg = <0x0 0x30260000 0x0 0x10000>;
+		clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
+		interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+		#thermal-sensor-cells = <0>;
+	};
+
+	thermal-zones {
+		/* cpu thermal */
+		cpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tmu>;
+			trips {
+				cpu_alert0: trip0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_crit0: trip1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+					<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	wdog1: wdog@30280000 {
+		compatible = "fsl,imx21-wdt";
+		reg = <0 0x30280000 0 0x10000>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
+		status = "disabled";
+	};
+
+	wdog2: wdog@30290000 {
+		compatible = "fsl,imx21-wdt";
+		reg = <0 0x30290000 0 0x10000>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
+		status = "disabled";
+	};
+
+	wdog3: wdog@302a0000 {
+		compatible = "fsl,imx21-wdt";
+		reg = <0 0x302a0000 0 0x10000>;
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
+		status = "disabled";
+	};
+
+	sdma2: dma-controller@302c0000 {
+		compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
+		reg = <0x0 0x302c0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
+			 <&clk IMX8MN_CLK_SDMA2_ROOT>;
+		clock-names = "ipg", "ahb";
+		#dma-cells = <3>;
+		fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+		fsl,ratio-1-1;
+		status = "okay";
+	};
+
+	sdma3: dma-controller@302b0000 {
+		compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
+		reg = <0x0 0x302b0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
+			 <&clk IMX8MN_CLK_SDMA3_ROOT>;
+		clock-names = "ipg", "ahb";
+		#dma-cells = <3>;
+		fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+		fsl,ratio-1-1;
+		status = "disabled";
+	};
+
+	iomuxc: pinctrl@30330000 {
+		compatible = "fsl,imx8mn-iomuxc";
+		reg = <0x0 0x30330000 0x0 0x10000>;
+	};
+
+	gpr: iomuxc-gpr@30340000 {
+		compatible = "fsl,imx8mn-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
+		reg = <0x0 0x30340000 0x0 0x10000>;
+	};
+
+	ocotp: ocotp-ctrl@30350000 {
+		compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
+		reg = <0 0x30350000 0 0x10000>;
+		clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
+		/* For nvmem subnodes */
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+
+	anatop: anatop@30360000 {
+		compatible = "fsl,imx8mn-anatop", "syscon", "simple-bus";
+		reg = <0x0 0x30360000 0x0 0x10000>;
+	};
+
+	snvs: snvs@30370000 {
+		compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
+		reg = <0x0 0x30370000 0x0 0x10000>;
+
+		snvs_rtc: snvs-rtc-lp{
+			compatible = "fsl,sec-v4.0-mon-rtc-lp";
+			regmap =<&snvs>;
+			offset = <0x34>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		snvs_pwrkey: snvs-powerkey {
+			compatible = "fsl,sec-v4.0-pwrkey";
+			regmap = <&snvs>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			linux,keycode = <KEY_POWER>;
+			wakeup-source;
+		};
+	};
+
+	clk: clock-controller@30380000 {
+		compatible = "fsl,imx8mn-ccm";
+		reg = <0x0 0x30380000 0x0 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
+			 <&clk_ext3>, <&clk_ext4>;
+		clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+			      "clk_ext3", "clk_ext4";
+	};
+
+	src: src@30390000 {
+		compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
+		reg = <0x0 0x30390000 0x0 0x10000>;
+		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+		#reset-cells = <1>;
+	};
+
+	pwm1: pwm@30660000 {
+		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x30660000 0x0 0x10000>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
+			<&clk IMX8MN_CLK_PWM1_ROOT>;
+		clock-names = "ipg", "per";
+		#pwm-cells = <2>;
+		status = "disabled";
+	};
+
+	pwm2: pwm@30670000 {
+		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x30670000 0x0 0x10000>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
+			<&clk IMX8MN_CLK_PWM2_ROOT>;
+		clock-names = "ipg", "per";
+		#pwm-cells = <2>;
+		status = "disabled";
+	};
+
+	pwm3: pwm@30680000 {
+		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x30680000 0x0 0x10000>;
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
+			<&clk IMX8MN_CLK_PWM3_ROOT>;
+		clock-names = "ipg", "per";
+		#pwm-cells = <2>;
+		status = "disabled";
+	};
+
+	pwm4: pwm@30690000 {
+		compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x30690000 0x0 0x10000>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
+			<&clk IMX8MN_CLK_PWM4_ROOT>;
+		clock-names = "ipg", "per";
+		#pwm-cells = <2>;
+		status = "disabled";
+	};
+
+	system_counter: timer@306a0000 {
+		compatible = "nxp,sysctr-timer";
+		reg = <0x0 0x306a0000 0x0 0x10000>, /* system-counter-rd base */
+		      <0x0 0x306b0000 0x0 0x10000>, /* system-counter-cmp base */
+		      <0x0 0x306c0000 0x0 0x10000>; /* system-counter-ctrl base */
+		clock-frequency = <8000000>;
+		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	ecspi1: ecspi@30820000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+		reg = <0x0 0x30820000 0x0 0x10000>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
+			<&clk IMX8MN_CLK_ECSPI1_ROOT>;
+		clock-names = "ipg", "per";
+		dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	ecspi2: ecspi@30830000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+		reg = <0x0 0x30830000 0x0 0x10000>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
+			<&clk IMX8MN_CLK_ECSPI2_ROOT>;
+		clock-names = "ipg", "per";
+		dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	ecspi3: ecspi@30840000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+		reg = <0x0 0x30840000 0x0 0x10000>;
+		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
+			<&clk IMX8MN_CLK_ECSPI3_ROOT>;
+		clock-names = "ipg", "per";
+		dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	uart1: serial@30860000 {
+		compatible = "fsl,imx8mm-uart",
+			     "fsl,imx6q-uart", "fsl,imx21-uart";
+		reg = <0x0 0x30860000 0x0 0x10000>;
+		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
+			<&clk IMX8MN_CLK_UART1_ROOT>;
+		clock-names = "ipg", "per";
+		dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	uart3: serial@30880000 {
+		compatible = "fsl,imx8mm-uart",
+			     "fsl,imx6q-uart", "fsl,imx21-uart";
+		reg = <0x0 0x30880000 0x0 0x10000>;
+		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
+			<&clk IMX8MN_CLK_UART3_ROOT>;
+		clock-names = "ipg", "per";
+		dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	uart2: serial@30890000 {
+		compatible = "fsl,imx8mm-uart",
+			     "fsl,imx6q-uart", "fsl,imx21-uart";
+		reg = <0x0 0x30890000 0x0 0x10000>;
+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
+			<&clk IMX8MN_CLK_UART2_ROOT>;
+		clock-names = "ipg", "per";
+		status = "disabled";
+	};
+
+	i2c1: i2c@30a20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+		reg = <0x0 0x30a20000 0x0 0x10000>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@30a30000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+		reg = <0x0 0x30a30000 0x0 0x10000>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@30a40000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+		reg = <0x0 0x30a40000 0x0 0x10000>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
+		status = "disabled";
+	};
+
+	i2c4: i2c@30a50000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+		reg = <0x0 0x30a50000 0x0 0x10000>;
+		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
+		status = "disabled";
+	};
+
+	uart4: serial@30a60000 {
+		compatible = "fsl,imx8mq-uart",
+			     "fsl,imx6q-uart", "fsl,imx21-uart";
+		reg = <0x0 0x30a60000 0x0 0x10000>;
+		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
+			<&clk IMX8MN_CLK_UART4_ROOT>;
+		clock-names = "ipg", "per";
+		dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	imx_rpmsg: imx_rpmsg {
+		compatible = "fsl,rpmsg-bus", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		mu: mu@30aa0000 {
+			compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
+			reg = <0x0 0x30aa0000 0x0 0x10000>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8MN_CLK_MU_ROOT>;
+			clock-names = "mu";
+			status = "disabled";
+		};
+
+		rpmsg: rpmsg{
+			compatible = "fsl,imx8qm-rpmsg";
+			status = "disabled";
+		};
+	};
+
+	usdhc1: mmc@30b40000 {
+		compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
+		reg = <0x0 0x30b40000 0x0 0x10000>;
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_DUMMY>,
+			 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
+			 <&clk IMX8MN_CLK_USDHC1_ROOT>;
+		clock-names = "ipg", "ahb", "per";
+		assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
+		assigned-clock-rates = <400000000>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		bus-width = <4>;
+		status = "disabled";
+	};
+
+	usdhc2: mmc@30b50000 {
+		compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
+		reg = <0x0 0x30b50000 0x0 0x10000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_DUMMY>,
+			 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
+			 <&clk IMX8MN_CLK_USDHC2_ROOT>;
+		clock-names = "ipg", "ahb", "per";
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		bus-width = <4>;
+		status = "disabled";
+	};
+
+	usdhc3: mmc@30b60000 {
+		compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
+		reg = <0x0 0x30b60000 0x0 0x10000>;
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_DUMMY>,
+			 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
+			 <&clk IMX8MN_CLK_USDHC3_ROOT>;
+		clock-names = "ipg", "ahb", "per";
+		assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
+		assigned-clock-rates = <400000000>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		bus-width = <4>;
+		status = "disabled";
+	};
+
+	flexspi: flexspi@30bb0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8mm-flexspi";
+		reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
+		reg-names = "FlexSPI", "FlexSPI-memory";
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_QSPI_ROOT>;
+		clock-names = "fspi";
+		assigned-clock-rates = <80000000>;
+		assigned-clocks = <&clk IMX8MN_CLK_QSPI>;
+		assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>;
+		status = "disabled";
+	};
+
+	sdma1: dma-controller@30bd0000 {
+		compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
+		reg = <0x0 0x30bd0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
+			 <&clk IMX8MN_CLK_SDMA1_ROOT>;
+		clock-names = "ipg", "ahb";
+		#dma-cells = <3>;
+		fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+		status = "okay";
+	};
+
+	fec1: ethernet@30be0000 {
+		compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
+		reg = <0x0 0x30be0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
+			 <&clk IMX8MN_CLK_ENET1_ROOT>,
+			 <&clk IMX8MN_CLK_ENET_TIMER>,
+			 <&clk IMX8MN_CLK_ENET_REF>,
+			 <&clk IMX8MN_CLK_ENET_PHY_REF>;
+		clock-names = "ipg", "ahb", "ptp",
+			"enet_clk_ref", "enet_out";
+		assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
+				  <&clk IMX8MN_CLK_ENET_TIMER>,
+				  <&clk IMX8MN_CLK_ENET_REF>,
+				  <&clk IMX8MN_CLK_ENET_TIMER>;
+		assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
+					 <&clk IMX8MN_SYS_PLL2_100M>,
+					 <&clk IMX8MN_SYS_PLL2_125M>;
+		assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+		stop-mode = <&gpr 0x10 3>;
+		fsl,num-tx-queues=<3>;
+		fsl,num-rx-queues=<3>;
+		fsl,wakeup_irq = <2>;
+		status = "disabled";
+	};
+
+	lcdif: lcd-controller@32E00000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8mm-lcdif";
+		reg = <0x0 0x32e00000 0x0 0x10000>;
+		clocks = <&clk IMX8MN_CLK_DISP_PIXEL>,
+			 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+			 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+		clock-names = "pix", "disp-axi", "disp-apb";
+		assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>,
+				  <&clk IMX8MN_CLK_DISP_AXI>,
+				  <&clk IMX8MN_CLK_DISP_APB>;
+		assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>,
+					 <&clk IMX8MN_SYS_PLL2_1000M>,
+					 <&clk IMX8MN_SYS_PLL1_800M>;
+		assigned-clock-rate = <594000000>, <500000000>, <200000000>;
+		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+		lcdif-gpr = <&dispmix_gpr>;
+		status = "disabled";
+
+		lcdif_disp0: port@0 {
+			reg = <0>;
+
+			lcdif_to_dsim: endpoint {
+				remote-endpoint = <&dsim_from_lcdif>;
+			};
+		};
+	};
+
+	mipi_dsi: mipi_dsi@32E10000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8mm-mipi-dsim";
+		reg = <0x0 0x32e10000 0x0 0x400>;
+		clocks = <&clk IMX8MN_CLK_DSI_CORE>,
+			 <&clk IMX8MN_CLK_DSI_PHY_REF>;
+		clock-names = "cfg", "pll-ref";
+		assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
+				  <&clk IMX8MN_CLK_DSI_PHY_REF>;
+		assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
+					 <&clk IMX8MN_VIDEO_PLL1_OUT>;
+		assigned-clock-rates = <266000000>, <594000000>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		dsi-gpr = <&dispmix_gpr>;
+		status = "disabled";
+
+		port@0 {
+			dsim_from_lcdif: endpoint {
+				remote-endpoint = <&lcdif_to_dsim>;
+			};
+		};
+	};
+
+	display-subsystem {
+		compatible = "fsl,imx-display-subsystem";
+		ports = <&lcdif_disp0>;
+	};
+
+	cameradev: camera {
+		compatible = "fsl,mxc-md", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		isi_0: isi@0x32e20000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x32e20000 0x0 0x2000>;
+		};
+
+		isi_1: isi@0x32e22000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x32e22000 0x0 0x2000>;
+		};
+
+		isi_2: isi@0x32e24000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x32e24000 0x0 0x2000>;
+		};
+
+		isi_3: isi@0x32e26000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x32e26000 0x0 0x2000>;
+		};
+	};
+
+	dispmix_gpr: display-gpr@32e28000 {
+		compatible = "fsl, imx8mm-iomuxc-gpr", "syscon";
+		reg = <0x0 0x32e28000 0x0 0x100>;
+	};
+
+	mipi_csi_1: mipi_csi@32e30000 {
+		compatible = "fsl,imx8mm-mipi-csi";
+		reg = <0x0 0x32e30000 0x0 0x1000>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <333000000>;
+		clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>,
+			<&clk IMX8MN_CLK_CSI1_PHY_REF>,
+			<&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+			<&clk IMX8MN_CLK_DISP_APB_ROOT>;
+		clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb";
+		bus-width = <4>;
+		csi-gpr = <&dispmix_gpr>;
+		status = "disabled";
+	};
+
+	usbotg1: usb@32e40000 {
+		compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
+		reg = <0x0 0x32e40000 0x0 0x200>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
+		clock-names = "usb1_ctrl_root_clk";
+		assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
+				  <&clk IMX8MN_CLK_USB_CORE_REF>;
+		assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
+					 <&clk IMX8MN_SYS_PLL1_100M>;
+		fsl,usbphy = <&usbphynop1>;
+		fsl,usbmisc = <&usbmisc1 0>;
+		status = "disabled";
+	};
+
+	usbphynop1: usbphynop1 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
+		assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
+		assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
+		clock-names = "main_clk";
+	};
+
+	usbmisc1: usbmisc@32e40200 {
+		#index-cells = <1>;
+		compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+		reg = <0x0 0x32e40200 0x0 0x200>;
+	};
+
+	dma_apbh: dma-apbh@33000000 {
+		compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+		reg = <0 0x33000000 0 0x2000>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+		#dma-cells = <1>;
+		dma-channels = <4>;
+		clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+	};
+
+	gpmi: gpmi-nand@33002000{
+		compatible = "fsl,imx7d-gpmi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>;
+		reg-names = "gpmi-nand", "bch";
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "bch";
+		clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
+			<&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+		clock-names = "gpmi_io", "gpmi_bch_apb";
+		dmas = <&dma_apbh 0>;
+		dma-names = "rx-tx";
+		status = "disabled";
+	};
+
+	gpu: gpu@38000000 {
+		compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu";
+		reg = <0x0 0x38000000 0 0x40000>, <0x0 0x40000000 0x0 0x40000000>, <0x0 0x0 0x0 0x80000000>;
+		reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_3d";
+		clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+			<&clk IMX8MN_CLK_GPU_SHADER_DIV>,
+			<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+			<&clk IMX8MN_CLK_GPU_AHB>;
+		clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk";
+		assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>,
+				<&clk IMX8MN_CLK_GPU_SHADER_SRC>,
+				<&clk IMX8MN_CLK_GPU_AXI>,
+				<&clk IMX8MN_CLK_GPU_AHB>,
+				<&clk IMX8MN_GPU_PLL>,
+				<&clk IMX8MN_CLK_GPU_CORE_DIV>,
+				<&clk IMX8MN_CLK_GPU_SHADER_DIV>;
+		assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
+					<&clk IMX8MN_GPU_PLL_OUT>,
+					<&clk IMX8MN_SYS_PLL1_800M>,
+					<&clk IMX8MN_SYS_PLL1_800M>;
+		assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1000000000>,
+					<500000000>, <500000000>;
+		depth-compression = <0>;
+		status = "disabled";
+	};
+
+	dma_cap: dma_cap {
+		compatible = "dma-capability";
+		only-dma-mask32 = <1>;
+	};
+
+	imx_ion {
+		compatible = "fsl,mxc-ion";
+		fsl,heap-id = <0>;
+	};
+};
+
+&A53_0 {
+	operating-points = <
+		/* kHz    uV */
+		1500000 1000000
+		1400000 900000
+		1200000 800000
+	>;
+	clocks = <&clk IMX8MN_CLK_A53_DIV>, <&clk IMX8MN_CLK_A53_SRC>,
+		<&clk IMX8MN_ARM_PLL>, <&clk IMX8MN_ARM_PLL_OUT>,
+		<&clk IMX8MN_SYS_PLL1_800M>;
+	clock-names = "a53", "arm_a53_src", "arm_pll",
+		"arm_pll_out", "sys1_pll_800m";
+	clock-latency = <61036>;
+	#cooling-cells = <2>;
+};