diff options
| author | Robert Chiras <robert.chiras@nxp.com> | 2018-11-26 14:35:12 +0200 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:36:05 +0800 |
| commit | f7743a67d1493f423a336af5e8a68970a8aacb2f (patch) | |
| tree | 1b2ad2352414137fc0cb86e44757141f0947343d /arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi | |
| parent | b9e3b7421f14447e09ce7031a48a098a829f9adb (diff) | |
MLK-17537-11: arch: arm64: fsl-imx8mq-evk: Reconfigure LCDIF, DCSS & DSI clocks
Reconfigure the LCDIF, DCSS and DSI clocks such that we can use
mode_valid to determine which mode can be supported or not by a specific
display pipe (DCSS+DSI or LCDIF+DSI).
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi | 31 |
1 files changed, 9 insertions, 22 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi index d801dba4d92e..7d124d3d3e30 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi @@ -30,24 +30,22 @@ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_CLK_DC_PIXEL>, - <&clk IMX8MQ_CLK_DUMMY>, - <&clk IMX8MQ_CLK_DISP_DTRC>; - clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc"; + <&clk IMX8MQ_CLK_DISP_DTRC>, + <&clk IMX8MQ_VIDEO_PLL1>, + <&clk IMX8MQ_CLK_27M>, + <&clk IMX8MQ_CLK_25M>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll", + "pll_src1", "pll_src2"; assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>, <&clk IMX8MQ_CLK_DISP_AXI>, - <&clk IMX8MQ_CLK_DISP_RTRM>, - <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, - <&clk IMX8MQ_VIDEO_PLL1>; + <&clk IMX8MQ_CLK_DISP_RTRM>; assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_CLK_25M>; + <&clk IMX8MQ_SYS1_PLL_800M>; assigned-clock-rates = <600000000>, <800000000>, - <0>, - <400000000>, - <599999999>; + <400000000>; dcss_disp0: port@0 { reg = <0>; @@ -64,17 +62,6 @@ &mipi_dsi { status = "okay"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>, - <&clk IMX8MQ_CLK_DSI_CORE>, - <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, - <&clk IMX8MQ_VIDEO_PLL1>; - assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, - <&clk IMX8MQ_SYS1_PLL_266M>, - <&clk IMX8MQ_CLK_25M>; - assigned-clock-rates = <24000000>, - <266000000>, - <0>, - <599999999>; port@1 { mipi_dsi_in: endpoint { |