diff options
| author | Abel Vesa <abel.vesa@nxp.com> | 2018-10-02 16:52:12 +0300 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:34:26 +0800 |
| commit | db12eaef1127f23effbdc2c68860342d3be3e1e6 (patch) | |
| tree | 29e999cd2cfc99cb77294ed0cc9f5ddf837bf32f /arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts | |
| parent | d332e11b65bcab036b8a464f905b18b7e6e2a3a0 (diff) | |
clk: imx8mq: Switch to newly added composite-8m clock
This needs to be one individual change since otherwise the driver
and the dtbs won't build anymore. This updates all the dts and dtsi files,
the clock index defines and the imx8mq clock driver itself
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts index 13ce6b7e1439..e74f353b4d0f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts @@ -26,14 +26,13 @@ }; &clk { - init-on-array = <IMX8MQ_CLK_DRAM_CORE IMX8MQ_CLK_AHB_CG - IMX8MQ_CLK_NOC_CG IMX8MQ_CLK_NOC_APB_CG - IMX8MQ_CLK_USB_BUS_CG - IMX8MQ_CLK_MAIN_AXI_CG IMX8MQ_CLK_A53_CG - IMX8MQ_CLK_AUDIO_AHB_DIV IMX8MQ_CLK_TMU_ROOT - IMX8MQ_CLK_DRAM_APB_DIV - IMX8MQ_CLK_NOC_CG IMX8MQ_CLK_NOC_APB_CG - IMX8MQ_CLK_NAND_USDHC_BUS_CG>; + init-on-array = <IMX8MQ_CLK_DRAM_CORE IMX8MQ_CLK_AHB + IMX8MQ_CLK_NOC IMX8MQ_CLK_NOC_APB + IMX8MQ_CLK_USB_BUS + IMX8MQ_CLK_MAIN_AXI IMX8MQ_CLK_A53_CG + IMX8MQ_CLK_AUDIO_AHB IMX8MQ_CLK_TMU_ROOT + IMX8MQ_CLK_DRAM_APB + IMX8MQ_CLK_NAND_USDHC_BUS>; }; &iomuxc { @@ -91,8 +90,8 @@ &uart1 { /* uart2 is used by the 2nd OS, so configure pin and clk */ pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>; - assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>, - <&clk IMX8MQ_CLK_UART2_SRC>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>, + <&clk IMX8MQ_CLK_UART2>; assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, <&clk IMX8MQ_CLK_25M>; }; |