diff options
| author | Viorel Suman <viorel.suman@nxp.com> | 2017-08-24 14:52:03 +0300 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:28:15 +0800 |
| commit | 6d7f3db6aae7497d3fd1ae08b43d5bc421809fd8 (patch) | |
| tree | fbcdf038c5b99220a5dac055550086c0771f0496 /arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | |
| parent | 99ef0d2b623de0b909cef328fa54396eee7c4d8d (diff) | |
MLK-16275-2: ARM64: dts: imx8qm/qxp: Sync ESAI0 and AMIX SAIs rates
The ESAI0 and AMIX SAIs rates need to be the same for the
common and master clocks in the clock tree given the existing
clock rates store/restore functionality and the asynchronous
nature of the drivers "probe" method invocation.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts index e6a870c2ae7d..2864fb5479d2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts @@ -101,7 +101,7 @@ }; &asrc1 { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; @@ -114,7 +114,7 @@ <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>; assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <786432000>, <24576000>, <24576000>, <24576000>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; status = "okay"; }; @@ -125,7 +125,7 @@ <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, <&clk IMX8QM_AUD_SAI_6_MCLK>; assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <786432000>, <49152000>, <49152000>, <49152000>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; fsl,sai-asynchronous; fsl,txm-rxs; status = "okay"; @@ -138,7 +138,7 @@ <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, <&clk IMX8QM_AUD_SAI_7_MCLK>; assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; - assigned-clock-rates = <0>, <786432000>, <49152000>, <49152000>, <49152000>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>; fsl,sai-asynchronous; fsl,txm-rxs; status = "okay"; |