diff options
| author | Shengjiu Wang <shengjiu.wang@freescale.com> | 2017-09-01 13:28:23 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:28:22 +0800 |
| commit | fc15e87741a2f6c573e949833522322b4ff06010 (patch) | |
| tree | 05c375c564ffe790632e47e5bcd867fb7c1aeee5 /arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | |
| parent | 7519e7b91dd3b12f475b4deb4533840591c8e5f7 (diff) | |
MLK-16350-1: ARM64: dts: add the clocks for each node
In current design, the assigned-clock-rates is bind with
each device node, even they are using same parent clocks.
so add clocks for each device.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts index 58783aba912f..f535b407ef13 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts @@ -96,12 +96,20 @@ }; &asrc0 { + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; fsl,asrc-rate = <48000>; status = "okay"; }; &asrc1 { fsl,asrc-rate = <48000>; + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <24576000>; status = "okay"; }; |