diff options
| author | Oleksandr Suvorov <oleksandr.suvorov@toradex.com> | 2021-03-26 20:29:54 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2021-03-26 22:10:44 +0000 |
| commit | 2eef26f5cb220742d43fc57b1063a523211d3811 (patch) | |
| tree | 0ca00d78c4e96e6d4983587753f76d26e898fa33 /arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi | |
| parent | 1f91c764a7d575e193409d54a47b5e5220b198fe (diff) | |
arm64: dts: colibri-imx8x: prepare pins for LVDS tranceiver
Toradex board Iris v2.0A has an LVDS tranceiver to convert LCD signal
to LVDS. It is configured with 4 signals. Add corresponding pins into
the separate pingroup to be able to manage the tranceiver.
Related-to: ELB-3876
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi index 696c1b3e15ad..e26c6c959826 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi @@ -708,10 +708,8 @@ IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ - IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ - IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ @@ -902,6 +900,17 @@ >; }; + /* LVDS converter on Iris v2.0 */ + pinctrl_lvds_converter: lcd-lvds { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x20 /* SODIMM 55 */ + /* 6B/8B mode. Select LOW - 8B mode (24bit) */ + IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x20 /* SODIMM 63 */ + IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ + IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ + >; + }; + /* USB Host Power Enable */ pinctrl_usbh1_reg: usbh1-reg { fsl,pins = < |