summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/freescale
diff options
context:
space:
mode:
authorAbel Vesa <abel.vesa@nxp.com>2018-10-02 16:52:12 +0300
committerJason Liu <jason.hui.liu@nxp.com>2019-02-12 10:34:26 +0800
commitdb12eaef1127f23effbdc2c68860342d3be3e1e6 (patch)
tree29e999cd2cfc99cb77294ed0cc9f5ddf837bf32f /arch/arm64/boot/dts/freescale
parentd332e11b65bcab036b8a464f905b18b7e6e2a3a0 (diff)
clk: imx8mq: Switch to newly added composite-8m clock
This needs to be one individual change since otherwise the driver and the dtbs won't build anymore. This updates all the dts and dtsi files, the clock index defines and the imx8mq clock driver itself Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts5
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts14
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dtsi12
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi16
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dtsi6
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts5
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts19
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts48
-rwxr-xr-xarch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi114
11 files changed, 112 insertions, 131 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts
index 58926e2efadf..2f9f6c660a65 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts
@@ -327,7 +327,7 @@
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts
index cf93e3bebc97..9679a76599fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts
@@ -316,7 +316,7 @@
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts
index d5b28bce186c..359894e53887 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-ak4497.dts
@@ -85,10 +85,9 @@
pinctrl-0 = <&pinctrl_sai1_pcm>;
pinctrl-1 = <&pinctrl_sai1_dsd>;
pinctrl-2 = <&pinctrl_sai1_dsd512>;
- assigned-clocks = <&clk IMX8MQ_CLK_SAI1_SRC>,
- <&clk IMX8MQ_CLK_SAI1_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL2_OUT>;
- assigned-clock-rates = <0>, <45158400>;
+ assigned-clock-rates = <45158400>;
fsl,sai-multi-lane;
fsl,dataline,dsd = <0xff 0x11>;
dmas = <&sdma2 8 26 0>, <&sdma2 9 26 0>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts
index a4f2005b0884..da8e86582573 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-b3.dts
@@ -26,12 +26,11 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi_rst>;
- clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ clocks = <&clk IMX8MQ_CLK_CLKO2>;
clock-names = "csi_mclk";
- assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>,
- <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
- assigned-clock-rates = <0>, <20000000>;
+ assigned-clock-rates = <20000000>;
csi_id = <0>;
pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
mclk = <20000000>;
@@ -49,12 +48,11 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi2_pwn>;
- clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ clocks = <&clk IMX8MQ_CLK_CLKO2>;
clock-names = "csi_mclk";
- assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>,
- <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
- assigned-clock-rates = <0>, <20000000>;
+ assigned-clock-rates = <20000000>;
csi_id = <1>;
pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
mclk = <20000000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dtsi
index 640674f9c32b..77a612bd6a1b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-adv7535.dtsi
@@ -29,20 +29,18 @@
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
- <&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
+ <&clk IMX8MQ_CLK_DC_PIXEL>,
<&clk IMX8MQ_CLK_DUMMY>,
- <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
+ <&clk IMX8MQ_CLK_DISP_DTRC>;
clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
- assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
- <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
- <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
- <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>,
+ <&clk IMX8MQ_CLK_DISP_AXI>,
+ <&clk IMX8MQ_CLK_DISP_RTRM>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
assigned-clock-rates = <594000000>,
<800000000>,
- <400000000>,
<400000000>;
dcss_disp0: port@0 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi
index 9215b6d8dbc2..969be8208a9d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dtsi
@@ -29,16 +29,15 @@
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
- <&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
+ <&clk IMX8MQ_CLK_DC_PIXEL>,
<&clk IMX8MQ_CLK_DUMMY>,
- <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
+ <&clk IMX8MQ_CLK_DISP_DTRC>;
clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
- assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
- <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
- <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
+ assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>,
+ <&clk IMX8MQ_CLK_DISP_AXI>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
- <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
+ <&clk IMX8MQ_CLK_DISP_RTRM>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
@@ -46,7 +45,6 @@
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <600000000>,
<800000000>,
- <400000000>,
<0>,
<400000000>,
<599999999>;
@@ -66,8 +64,8 @@
&mipi_dsi {
status = "okay";
- assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
- <&clk IMX8MQ_CLK_DSI_CORE_SRC>,
+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+ <&clk IMX8MQ_CLK_DSI_CORE>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dtsi
index 3b1a115f317f..325ed264f5db 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-lcdif-rm67191.dtsi
@@ -38,7 +38,7 @@
status = "okay";
max-res = <1080>, <1920>;
- assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>,
+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
@@ -62,8 +62,8 @@
status = "okay";
as_bridge;
sync-pol = <1>;
- assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
- <&clk IMX8MQ_CLK_DSI_CORE_SRC>,
+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+ <&clk IMX8MQ_CLK_DSI_CORE>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts
index a2e84eea463b..24e9c6bd416c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-pdm.dts
@@ -39,9 +39,8 @@
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MQ_CLK_SAI3_SRC>,
- <&clk IMX8MQ_CLK_SAI3_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <24576000>;
+ assigned-clock-rates = <24576000>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts
index 13ce6b7e1439..e74f353b4d0f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts
@@ -26,14 +26,13 @@
};
&clk {
- init-on-array = <IMX8MQ_CLK_DRAM_CORE IMX8MQ_CLK_AHB_CG
- IMX8MQ_CLK_NOC_CG IMX8MQ_CLK_NOC_APB_CG
- IMX8MQ_CLK_USB_BUS_CG
- IMX8MQ_CLK_MAIN_AXI_CG IMX8MQ_CLK_A53_CG
- IMX8MQ_CLK_AUDIO_AHB_DIV IMX8MQ_CLK_TMU_ROOT
- IMX8MQ_CLK_DRAM_APB_DIV
- IMX8MQ_CLK_NOC_CG IMX8MQ_CLK_NOC_APB_CG
- IMX8MQ_CLK_NAND_USDHC_BUS_CG>;
+ init-on-array = <IMX8MQ_CLK_DRAM_CORE IMX8MQ_CLK_AHB
+ IMX8MQ_CLK_NOC IMX8MQ_CLK_NOC_APB
+ IMX8MQ_CLK_USB_BUS
+ IMX8MQ_CLK_MAIN_AXI IMX8MQ_CLK_A53_CG
+ IMX8MQ_CLK_AUDIO_AHB IMX8MQ_CLK_TMU_ROOT
+ IMX8MQ_CLK_DRAM_APB
+ IMX8MQ_CLK_NAND_USDHC_BUS>;
};
&iomuxc {
@@ -91,8 +90,8 @@
&uart1 {
/* uart2 is used by the 2nd OS, so configure pin and clk */
pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>;
- assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>,
- <&clk IMX8MQ_CLK_UART2_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>,
+ <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
<&clk IMX8MQ_CLK_25M>;
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
index af0f7596ec65..bc92ec5403f5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk.dts
@@ -584,12 +584,11 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>;
- clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ clocks = <&clk IMX8MQ_CLK_CLKO2>;
clock-names = "csi_mclk";
- assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>,
- <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
- assigned-clock-rates = <0>, <20000000>;
+ assigned-clock-rates = <20000000>;
csi_id = <1>;
pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
mclk = <20000000>;
@@ -615,12 +614,11 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1_pwn>;
- clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ clocks = <&clk IMX8MQ_CLK_CLKO2>;
clock-names = "csi_mclk";
- assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>,
- <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
- assigned-clock-rates = <0>, <20000000>;
+ assigned-clock-rates = <20000000>;
csi_id = <0>;
pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
mclk = <20000000>;
@@ -713,7 +711,7 @@
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
@@ -736,7 +734,7 @@
&uart3 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
- assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
fsl,uart-has-rtscts;
resets = <&modem_reset>;
@@ -799,10 +797,9 @@
pinctrl-0 = <&pinctrl_sai1_pcm>;
pinctrl-1 = <&pinctrl_sai1_pcm_b2m>;
pinctrl-2 = <&pinctrl_sai1_dsd>;
- assigned-clocks = <&clk IMX8MQ_CLK_SAI1_SRC>,
- <&clk IMX8MQ_CLK_SAI1_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <49152000>;
+ assigned-clock-rates = <49152000>;
clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_SAI1_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
@@ -817,28 +814,25 @@
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
- assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>,
- <&clk IMX8MQ_CLK_SAI2_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <24576000>;
+ assigned-clock-rates = <24576000>;
status = "okay";
};
&sai4 {
- assigned-clocks = <&clk IMX8MQ_CLK_SAI4_SRC>,
- <&clk IMX8MQ_CLK_SAI4_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI4>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <24576000>;
+ assigned-clock-rates = <24576000>;
status = "okay";
};
&sai5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
- assigned-clocks = <&clk IMX8MQ_CLK_SAI5_SRC>,
- <&clk IMX8MQ_CLK_SAI5_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <49152000>;
+ assigned-clock-rates = <49152000>;
clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_SAI5_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
@@ -851,18 +845,16 @@
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
- assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1_SRC>,
- <&clk IMX8MQ_CLK_SPDIF1_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <24576000>;
+ assigned-clock-rates = <24576000>;
status = "okay";
};
&spdif2 {
- assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2_SRC>,
- <&clk IMX8MQ_CLK_SPDIF2_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <24576000>;
+ assigned-clock-rates = <24576000>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
index 819b079305ec..5c59a55890ca 100755
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
@@ -114,13 +114,13 @@
busfreq { /* BUSFREQ */
compatible = "fsl,imx_busfreq";
- clocks = <&clk IMX8MQ_DRAM_PLL1>, <&clk IMX8MQ_CLK_DRAM_ALT_SRC>,
- <&clk IMX8MQ_CLK_DRAM_APB_SRC>, <&clk IMX8MQ_CLK_DRAM_APB_PRE_DIV>,
+ clocks = <&clk IMX8MQ_DRAM_PLL1>, <&clk IMX8MQ_CLK_DRAM_ALT>,
+ <&clk IMX8MQ_CLK_DRAM_APB>, <&clk IMX8MQ_CLK_DRAM_APB>,
<&clk IMX8MQ_CLK_DRAM_CORE>, <&clk IMX8MQ_CLK_DRAM_ALT_ROOT>,
<&clk IMX8MQ_SYS1_PLL_40M>, <&clk IMX8MQ_SYS1_PLL_400M>,
<&clk IMX8MQ_SYS1_PLL_100M>, <&clk IMX8MQ_SYS1_PLL_800M>,
- <&clk IMX8MQ_CLK_NOC_DIV>, <&clk IMX8MQ_CLK_MAIN_AXI_SRC>,
- <&clk IMX8MQ_CLK_AHB_DIV>, <&clk IMX8MQ_CLK_25M>,
+ <&clk IMX8MQ_CLK_NOC>, <&clk IMX8MQ_CLK_MAIN_AXI>,
+ <&clk IMX8MQ_CLK_AHB>, <&clk IMX8MQ_CLK_25M>,
<&clk IMX8MQ_SYS2_PLL_333M>, <&clk IMX8MQ_SYS1_PLL_133M>;
clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div",
"dram_core", "dram_alt_root", "sys1_pll_40m", "sys1_pll_400m",
@@ -225,8 +225,8 @@
#power-domain-cells = <0>;
domain-id = <4>;
domain-name = "GPU_PD";
- clocks = <&clk IMX8MQ_CLK_GPU_AXI_DIV>, <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
- <&clk IMX8MQ_CLK_GPU_ROOT>, <&clk IMX8MQ_CLK_GPU_AHB_DIV>;
+ clocks = <&clk IMX8MQ_CLK_GPU_AXI>, <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
+ <&clk IMX8MQ_CLK_GPU_ROOT>, <&clk IMX8MQ_CLK_GPU_AHB>;
};
vpu_pd: gpc_power_domain@5 {
@@ -489,13 +489,13 @@
reg = <0x0 0x30a70000 0x0 0x1000>; /* MIPI CSI1 Controller base addr */
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>,
- <&clk IMX8MQ_CLK_CSI1_CORE_DIV>,
- <&clk IMX8MQ_CLK_CSI1_ESC_DIV>,
- <&clk IMX8MQ_CLK_CSI1_PHY_REF_DIV>;
+ <&clk IMX8MQ_CLK_CSI1_CORE>,
+ <&clk IMX8MQ_CLK_CSI1_ESC>,
+ <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
- assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE_DIV>,
- <&clk IMX8MQ_CLK_CSI1_PHY_REF_DIV>,
- <&clk IMX8MQ_CLK_CSI1_ESC_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
+ <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
+ <&clk IMX8MQ_CLK_CSI1_ESC>;
assigned-clock-rates = <133000000>, <100000000>, <66000000>;
power-domains = <&mipi_csi1_pd>;
csis-phy-reset = <&src 0x4c 7>;
@@ -508,13 +508,13 @@
reg = <0x0 0x30b60000 0x0 0x1000>; /* MIPI CSI2 Controller base addr */
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>,
- <&clk IMX8MQ_CLK_CSI2_CORE_DIV>,
- <&clk IMX8MQ_CLK_CSI2_ESC_DIV>,
- <&clk IMX8MQ_CLK_CSI2_PHY_REF_DIV>;
+ <&clk IMX8MQ_CLK_CSI2_CORE>,
+ <&clk IMX8MQ_CLK_CSI2_ESC>,
+ <&clk IMX8MQ_CLK_CSI2_PHY_REF>;
clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
- assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE_DIV>,
- <&clk IMX8MQ_CLK_CSI2_PHY_REF_DIV>,
- <&clk IMX8MQ_CLK_CSI2_ESC_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
+ <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
+ <&clk IMX8MQ_CLK_CSI2_ESC>;
assigned-clock-rates = <133000000>, <100000000>, <66000000>;
power-domains = <&mipi_csi2_pd>;
csis-phy-reset = <&src 0x50 7>;
@@ -549,18 +549,16 @@
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>,
- <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
+ <&clk IMX8MQ_CLK_DISP_DTRC>;
clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
- assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
- <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
- <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
- <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>,
+ <&clk IMX8MQ_CLK_DISP_AXI>,
+ <&clk IMX8MQ_CLK_DISP_RTRM>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>;
assigned-clock-rates = <594000000>,
<800000000>,
- <400000000>,
<400000000>;
status = "disabled";
@@ -597,9 +595,9 @@
lcdif: lcdif@30320000 {
compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
reg = <0x0 0x30320000 0x0 0x10000>;
- clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>;
+ clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
clock-names = "pix";
- assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
assigned-clock-rate = <594000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
@@ -626,11 +624,11 @@
compatible = "nwl,mipi-dsi";
reg = <0x0 0x30A00000 0x0 0x400>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>,
- <&clk IMX8MQ_CLK_DSI_AHB_DIV>,
+ clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+ <&clk IMX8MQ_CLK_DSI_AHB>,
<&clk IMX8MQ_CLK_DSI_IPG_DIV>;
clock-names = "phy_ref", "rx_esc", "tx_esc";
- assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
assigned-clock-rates = <80000000>;
phys = <&mipi_dsi_phy>;
@@ -647,11 +645,11 @@
mipi_dsi: mipi_dsi@30A00000 {
compatible = "fsl,imx8mq-mipi-dsi_drm";
- clocks = <&clk IMX8MQ_CLK_DSI_CORE_DIV>,
- <&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>;
+ clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
+ <&clk IMX8MQ_CLK_DSI_PHY_REF>;
clock-names = "core", "phy_ref";
- assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
- <&clk IMX8MQ_CLK_DSI_CORE_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+ <&clk IMX8MQ_CLK_DSI_CORE>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_266M>;
assigned-clock-rates = <594000000>, <266000000>;
@@ -761,7 +759,7 @@
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
<&clk IMX8MQ_CLK_25M>, /* rxtx0 */
- <&clk IMX8MQ_CLK_SPDIF1_DIV>, /* rxtx1 */
+ <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
@@ -868,7 +866,7 @@
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
<&clk IMX8MQ_CLK_25M>, /* rxtx0 */
- <&clk IMX8MQ_CLK_SPDIF2_DIV>, /* rxtx1 */
+ <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
<&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
@@ -914,7 +912,7 @@
reg = <0x0 0x381f0040 0x0 0x40>;
clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
clock-names = "usb_phy_root_clk";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
assigned-clock-rates = <100000000>;
status = "disabled";
@@ -927,8 +925,8 @@
ranges;
clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>,
- <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+ <&clk IMX8MQ_CLK_USB_CORE_REF>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
<&clk IMX8MQ_SYS1_PLL_100M>;
assigned-clock-rates = <500000000>, <100000000>;
@@ -956,7 +954,7 @@
reg = <0x0 0x382f0040 0x0 0x40>;
clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
clock-names = "usb_phy_root_clk";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
assigned-clock-rates = <100000000>;
status = "disabled";
@@ -969,8 +967,8 @@
ranges;
clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
clock-names = "usb2_ctrl_root_clk";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS_SRC>,
- <&clk IMX8MQ_CLK_USB_CORE_REF_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+ <&clk IMX8MQ_CLK_USB_CORE_REF>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
<&clk IMX8MQ_SYS1_PLL_100M>;
assigned-clock-rates = <500000000>, <100000000>;
@@ -995,10 +993,10 @@
reg = <0x0 0x30b40000 0x0 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>,
- <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step = <2>;
@@ -1012,7 +1010,7 @@
reg = <0x0 0x30b50000 0x0 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>,
- <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
@@ -1149,15 +1147,15 @@
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
<&clk IMX8MQ_CLK_ENET1_ROOT>,
- <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
- <&clk IMX8MQ_CLK_ENET_REF_DIV>,
- <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
+ <&clk IMX8MQ_CLK_ENET_TIMER>,
+ <&clk IMX8MQ_CLK_ENET_REF>,
+ <&clk IMX8MQ_CLK_ENET_PHY_REF>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
- assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
- <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
- <&clk IMX8MQ_CLK_ENET_REF_SRC>,
- <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
+ assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
+ <&clk IMX8MQ_CLK_ENET_TIMER>,
+ <&clk IMX8MQ_CLK_ENET_REF>,
+ <&clk IMX8MQ_CLK_ENET_TIMER>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
<&clk IMX8MQ_SYS2_PLL_125M>;
@@ -1175,9 +1173,9 @@
reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_3d";
- clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, <&clk IMX8MQ_CLK_GPU_AXI_DIV>, <&clk IMX8MQ_CLK_GPU_AHB_DIV>;
+ clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, <&clk IMX8MQ_CLK_GPU_AXI>, <&clk IMX8MQ_CLK_GPU_AHB>;
clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk";
- assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, <&clk IMX8MQ_CLK_GPU_AXI_SRC>, <&clk IMX8MQ_CLK_GPU_AHB_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, <&clk IMX8MQ_CLK_GPU_AXI>, <&clk IMX8MQ_CLK_GPU_AHB>;
assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>;
assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>;
power-domains = <&gpu_pd>;
@@ -1238,7 +1236,7 @@
interrupt-names = "irq_hantro_g1", "irq_hantro_g2";
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
clock-names = "clk_hantro_g1", "clk_hantro_g2", "clk_hantro_bus";
- assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1_SRC>, <&clk IMX8MQ_CLK_VPU_G2_SRC>, <&clk IMX8MQ_CLK_VPU_BUS_SRC>;
+ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, <&clk IMX8MQ_CLK_VPU_G2>, <&clk IMX8MQ_CLK_VPU_BUS>;
assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>;
assigned-clock-rates = <600000000>, <600000000>, <800000000>;
power-domains = <&vpu_pd>;
@@ -1309,8 +1307,8 @@
<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
- <&clk IMX8MQ_CLK_PCIE1_AUX_CG>,
- <&clk IMX8MQ_CLK_PCIE1_PHY_CG>;
+ <&clk IMX8MQ_CLK_PCIE1_AUX>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
fsl,max-link-speed = <2>;
ctrl-id = <0>;
@@ -1339,8 +1337,8 @@
<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
- <&clk IMX8MQ_CLK_PCIE2_AUX_CG>,
- <&clk IMX8MQ_CLK_PCIE2_PHY_CG>;
+ <&clk IMX8MQ_CLK_PCIE2_AUX>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
fsl,max-link-speed = <2>;
ctrl-id = <1>;
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-04 16:30:30 +0000