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authorDominik Sliwa <dominik.sliwa@toradex.com>2017-10-10 13:59:54 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2017-12-21 01:48:30 +0100
commite7aa4161297414958e336a19930cfc518e613c6e (patch)
treeb2b9c1863da2f7b63ad74dfaacd5fb8f68892384 /arch/arm
parent7753763827bb50f4645622e83c47e192e0ba0194 (diff)
tegra: apalis_t30: colibri_t30: increase pwm clock
Incresed PWM base clock to 25.5MHz. This results in maximum 99.6Khz PWM out frequency which can be further divided by an integer divider. Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-tegra/board-apalis_t30.c2
-rw-r--r--arch/arm/mach-tegra/board-colibri_t30.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/board-apalis_t30.c b/arch/arm/mach-tegra/board-apalis_t30.c
index bfd9a5346f2c..ababdb86dd01 100644
--- a/arch/arm/mach-tegra/board-apalis_t30.c
+++ b/arch/arm/mach-tegra/board-apalis_t30.c
@@ -459,7 +459,7 @@ static struct tegra_clk_init_table apalis_t30_clk_init_table[] __initdata = {
{"i2s4", "pll_a_out0", 0, false},
{"pll_a", NULL, 564480000, true},
{"pll_m", NULL, 0, false},
- {"pwm", "pll_p", 3187500, false},
+ {"pwm", "pll_p", 25500000, false},
{"spdif_out", "pll_a_out0", 0, false},
{"vi", "pll_p", 0, false},
{"vi_sensor", "pll_p", 24000000, true},
diff --git a/arch/arm/mach-tegra/board-colibri_t30.c b/arch/arm/mach-tegra/board-colibri_t30.c
index ea72781a31fb..68f52c5b0506 100644
--- a/arch/arm/mach-tegra/board-colibri_t30.c
+++ b/arch/arm/mach-tegra/board-colibri_t30.c
@@ -465,7 +465,7 @@ static struct tegra_clk_init_table colibri_t30_clk_init_table[] __initdata = {
{"nor", "pll_p", 86500000, true},
{"pll_a", NULL, 564480000, true},
{"pll_m", NULL, 0, false},
- {"pwm", "pll_p", 3187500, false},
+ {"pwm", "pll_p", 25500000, false},
{"spdif_out", "pll_a_out0", 0, false},
{"vi", "pll_p", 0, false},
{NULL, NULL, 0, 0},