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authorIngo Molnar <mingo@elte.hu>2008-06-16 11:20:57 +0200
committerIngo Molnar <mingo@elte.hu>2008-06-16 11:20:57 +0200
commitfd2c17e1777d46cff14c25ea774a4d17459d188a (patch)
treee8299216de8e99418195ba64bcf8f679df3a66b3 /arch/blackfin/lib/ins.S
parent74e411cb6443d8bcb55fbe89fcc7a9ee574df91b (diff)
parent066519068ad2fbe98c7f45552b1f592903a9c8c8 (diff)
Merge branch 'linus' into x86/timerstip-x86-timers-2008-06-16_09.20_Mon
Diffstat (limited to 'arch/blackfin/lib/ins.S')
-rw-r--r--arch/blackfin/lib/ins.S21
1 files changed, 18 insertions, 3 deletions
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
index df7b8833a0c5..eba2343b1b59 100644
--- a/arch/blackfin/lib/ins.S
+++ b/arch/blackfin/lib/ins.S
@@ -7,7 +7,7 @@
* Description: Implementation of ins{bwl} for BlackFin processors using zero overhead loops.
*
* Modified:
- * Copyright 2004-2006 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
* Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
@@ -63,6 +63,23 @@ ENTRY(_insw)
RTS;
ENDPROC(_insw)
+ENTRY(_insw_8)
+ P0 = R0; /* P0 = port */
+ cli R3;
+ P1 = R1; /* P1 = address */
+ P2 = R2; /* P2 = count */
+ SSYNC;
+ LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
+.Lword8_loop_s: R0 = W[P0];
+ B[P1++] = R0;
+ R0 = R0 >> 8;
+ B[P1++] = R0;
+ NOP;
+.Lword8_loop_e: NOP;
+ sti R3;
+ RTS;
+ENDPROC(_insw_8)
+
ENTRY(_insb)
P0 = R0; /* P0 = port */
cli R3;
@@ -78,8 +95,6 @@ ENTRY(_insb)
RTS;
ENDPROC(_insb)
-
-
ENTRY(_insl_16)
P0 = R0; /* P0 = port */
cli R3;