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authorMichael Hennerich <michael.hennerich@analog.com>2009-09-25 09:03:21 +0000
committerMike Frysinger <vapier@gentoo.org>2009-12-15 00:14:00 -0500
commitd887a1ce285f03c689bb4fbbaf574160bb484c3e (patch)
treecb1bfea50d25294c7a4c1c886f1b0b5aab743016 /arch/blackfin/mach-common/cpufreq.c
parent21b03cfe4c50fd586bfebd06d852457c07f60c2b (diff)
Blackfin: cpufreq: use a constant latency
PLL_LOCKCNT applies only to the PLL programming sequence which does not apply to core and system clock dividers. Writes to PLL_DIV to change the CSEL/SSEL dividers take effect immediately. There is still overhead in software in writing the new dividers, so just use a value of 50us as this should be good enough. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common/cpufreq.c')
-rw-r--r--arch/blackfin/mach-common/cpufreq.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 01506504e6d0..3d18d2ba4786 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -138,7 +138,8 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
dpm_state_table[index].tscale);
}
- policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000;
+ policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
+
/*Now ,only support one cpu */
policy->cur = cclk;
cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);