diff options
| author | Steven Whitehouse <swhiteho@redhat.com> | 2006-05-12 10:48:52 -0400 |
|---|---|---|
| committer | Steven Whitehouse <swhiteho@redhat.com> | 2006-05-12 10:48:52 -0400 |
| commit | 7d63b54a65ce902f9aaa8efe8192aa3b983264d4 (patch) | |
| tree | 250a77bebe92cbd6edac70a649866044295876db /arch/i386/kernel/mpparse.c | |
| parent | fd88de569b802c4a04aaa6ee74667775f4aed8c6 (diff) | |
| parent | d8c3291c73b958243b33f8509d4507e76dafd055 (diff) | |
Merge branch 'master'
Diffstat (limited to 'arch/i386/kernel/mpparse.c')
| -rw-r--r-- | arch/i386/kernel/mpparse.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/i386/kernel/mpparse.c b/arch/i386/kernel/mpparse.c index 34d21e21e012..6b1392d33ed5 100644 --- a/arch/i386/kernel/mpparse.c +++ b/arch/i386/kernel/mpparse.c @@ -1130,7 +1130,17 @@ int mp_register_gsi (u32 gsi, int triggering, int polarity) */ int irq = gsi; if (gsi < MAX_GSI_NUM) { - if (gsi > 15) + /* + * Retain the VIA chipset work-around (gsi > 15), but + * avoid a problem where the 8254 timer (IRQ0) is setup + * via an override (so it's not on pin 0 of the ioapic), + * and at the same time, the pin 0 interrupt is a PCI + * type. The gsi > 15 test could cause these two pins + * to be shared as IRQ0, and they are not shareable. + * So test for this condition, and if necessary, avoid + * the pin collision. + */ + if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0)) gsi = pci_irq++; /* * Don't assign IRQ used by ACPI SCI |