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authorRalf Baechle <ralf@linux-mips.org>2007-10-11 23:46:09 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 23:46:09 +0100
commit91a2fcc88634663e9e13dcdfad0e4a860e64aeee (patch)
treea86b936f1057207d46e5a07ed826052ff640869a /arch/mips/au1000/common/irq.c
parent90b02340dcc6ce00bf22c48f4865915f5989e5e4 (diff)
[MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/au1000/common/irq.c')
-rw-r--r--arch/mips/au1000/common/irq.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index db2ba0dbfd5a..47949d6f2c10 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -65,8 +65,6 @@
#define EXT_INTC1_REQ1 5 /* IP 5 */
#define MIPS_TIMER_IP 7 /* IP 7 */
-extern void mips_timer_interrupt(void);
-
void (*board_init_irq)(void);
static DEFINE_SPINLOCK(irq_lock);
@@ -635,7 +633,7 @@ asmlinkage void plat_irq_dispatch(void)
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & CAUSEF_IP7)
- mips_timer_interrupt();
+ ll_timer_interrupt(63);
else if (pending & CAUSEF_IP2)
intc0_req0_irqdispatch();
else if (pending & CAUSEF_IP3)