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authorLinus Torvalds <torvalds@g5.osdl.org>2006-10-30 19:31:20 -0800
committerLinus Torvalds <torvalds@g5.osdl.org>2006-10-30 19:31:20 -0800
commit528ba4ef855bd184b7d68e3fa596b420fb4fa86a (patch)
tree9b7a296f2ae3942ca401bd099ae92d00bbe366a9 /arch/mips/emma2rh/markeins/irq_markeins.c
parentdf6c0cd9a872ebf2298f5d66d8c789f62dbe35fc (diff)
parent21e9ac7b2dd96dfca997313bae6d9a8f642635c7 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] MIPS doesn't need compat_sys_getdents. [MIPS] JMR3927: Fixup another victim of the irq pt_regs cleanup. [MIPS] EMMA 2 / Markeins: struct resource takes physical addresses. [MIPS] EMMA 2 / Markeins: Convert to name struct resource initialization. [MIPS] EMMA 2 / Markeins: Formitting fixes split from actual address fixes. [MIPS] EMMA 2 / Markeins: Fix build wreckage due to genirq wreckage. [MIPS] Ocelot G: Fix build error and numerous warnings. [MIPS] Fix return value of TXX9 SPI interrupt handler [MIPS] Au1000: Fix warning about unused variable. [MIPS] Wire up getcpu(2) and epoll_wait(2) syscalls. [MIPS] Make SB1 cache flushes not to use on_each_cpu [MIPS] Fix warning about unused definition in c-sb1.c [MIPS] SMTC: Make 8 the default number of processors. [MIPS] Oprofile: Fix MIPSxx counter number detection. [MIPS] Au1xx0 code sets incorrect mips_hpt_frequency [MIPS] Oprofile: fix on non-VSMP / non-SMTC SMP configurations.
Diffstat (limited to 'arch/mips/emma2rh/markeins/irq_markeins.c')
-rw-r--r--arch/mips/emma2rh/markeins/irq_markeins.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c
index f23ae9fcffa0..0b36eb001e62 100644
--- a/arch/mips/emma2rh/markeins/irq_markeins.c
+++ b/arch/mips/emma2rh/markeins/irq_markeins.c
@@ -86,7 +86,7 @@ void emma2rh_sw_irq_init(u32 irq_base)
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 2;
- irq_desc[i].handler = &emma2rh_sw_irq_controller;
+ irq_desc[i].chip = &emma2rh_sw_irq_controller;
}
emma2rh_sw_irq_base = irq_base;
@@ -166,7 +166,7 @@ void emma2rh_gpio_irq_init(u32 irq_base)
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 2;
- irq_desc[i].handler = &emma2rh_gpio_irq_controller;
+ irq_desc[i].chip = &emma2rh_gpio_irq_controller;
}
emma2rh_gpio_irq_base = irq_base;