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authorRalf Baechle <ralf@linux-mips.org>2009-02-28 09:44:28 +0000
committerRalf Baechle <ralf@linux-mips.org>2009-06-08 16:57:51 +0100
commit5636919b5c909fee54a6ef5226475ecae012ad02 (patch)
treec77fa89c56ee2d493fb82117ab5dbc5b28a8deeb /arch/mips/include/asm/cpu-info.h
parent3a553147eaad5d4de90ab1f695aa13ddbea684ec (diff)
MIPS: Outline udelay and fix a few issues.
Outlining fixes the issue were on certain CPUs such as the R10000 family the delay loop would need an extra cycle if it overlaps a cacheline boundary. The rewrite also fixes build errors with GCC 4.4 which was changed in way incompatible with the kernel's inline assembly. Relying on pure C for computation of the delay value removes the need for explicit. The price we pay is a slight slowdown of the computation - to be fixed on another day. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu-info.h')
-rw-r--r--arch/mips/include/asm/cpu-info.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 744cd8fb107f..126044308dec 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -39,8 +39,8 @@ struct cache_desc {
#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
struct cpuinfo_mips {
- unsigned long udelay_val;
- unsigned long asid_cache;
+ unsigned int udelay_val;
+ unsigned int asid_cache;
/*
* Capability and feature descriptor structure for MIPS CPU