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authorPaul Mackerras <paulus@samba.org>2009-03-06 16:27:10 +1100
committerPaul Mackerras <paulus@samba.org>2009-03-06 16:28:37 +1100
commitaabbaa6036fd847c583f585c6bae82b5a033e6c7 (patch)
tree097a73e1546b7396b49031ab5a3e1d4c1e7c5598 /arch/powerpc/kernel/perf_counter.c
parent86028598de16538f02519141756ccf4accfc29a6 (diff)
perfcounters/powerpc: add support for POWER5+ processors
Impact: more hardware support This adds the back-end for the PMU on the POWER5+ processors (i.e. GS, including GS DD3 aka POWER5++). This doesn't use the fixed-function PMC5 and PMC6 since they don't respect the freeze conditions and don't generate interrupts, as on POWER6. Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/kernel/perf_counter.c')
-rw-r--r--arch/powerpc/kernel/perf_counter.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c
index 4fec112386fc..162f3981fa27 100644
--- a/arch/powerpc/kernel/perf_counter.c
+++ b/arch/powerpc/kernel/perf_counter.c
@@ -826,6 +826,7 @@ void hw_perf_counter_setup(int cpu)
extern struct power_pmu ppc970_pmu;
extern struct power_pmu power5_pmu;
+extern struct power_pmu power5p_pmu;
extern struct power_pmu power6_pmu;
static int init_perf_counters(void)
@@ -848,6 +849,9 @@ static int init_perf_counters(void)
case PV_POWER5:
ppmu = &power5_pmu;
break;
+ case PV_POWER5p:
+ ppmu = &power5p_pmu;
+ break;
case 0x3e:
ppmu = &power6_pmu;
break;