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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-07-08 15:54:40 +1000
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2008-07-09 13:36:17 -0400
commit1bc54c03117b90716e0dedd7abb2a20405de65df (patch)
tree8e82fd610abaff36f1e20b5aaaf7bdeaee883aac /arch/powerpc/mm/fault.c
parentbeae4c03c0fe69cf7d57518aa0572ad21730b8be (diff)
powerpc: rework 4xx PTE access and TLB miss
This is some preliminary work to improve TLB management on SW loaded TLB powerpc platforms. This introduce support for non-atomic PTE operations in pgtable-ppc32.h and removes write back to the PTE from the TLB miss handlers. In addition, the DSI interrupt code no longer tries to fixup write permission, this is left to generic code, and _PAGE_HWWRITE is gone. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/mm/fault.c')
-rw-r--r--arch/powerpc/mm/fault.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 7b2510799266..1707d00331fc 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -306,7 +306,8 @@ good_area:
flush_dcache_icache_page(page);
set_bit(PG_arch_1, &page->flags);
}
- pte_update(ptep, 0, _PAGE_HWEXEC);
+ pte_update(ptep, 0, _PAGE_HWEXEC |
+ _PAGE_ACCESSED);
_tlbie(address, mm->context.id);
pte_unmap_unlock(ptep, ptl);
up_read(&mm->mmap_sem);