[PATCH] spufs: fix mailbox polling

Handling mailbox interrupts was broken in multiple respects,
the combination of which was hiding the bugs most of the time.

- The ibox interrupt mask was open initially even though there
  are no waiters on a newly created SPU.

- Acknowledging the mailbox interrupt did not work because
  it is level triggered and the mailbox data is never retrieved
  from inside the interrupt handler.

- The interrupt handler delivered interrupts with a disabled
  mask if another interrupt is triggered for the same class
  but a different mask.

- The poll function did not enable the interrupt if it had not
  been enabled, so we might run into the poll timeout if none of
  the other bugs saved us and no signal was delivered.

We probably still have a similar problem with blocking
read/write on mailbox files, but that will result in extra
wakeup in the worst case, not in incorrect behaviour.

Signed-off-by: Arnd Bergmann <arndb@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 8 insertions, 3 deletions

diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c
index 8abd4bd19665..f9da79eb3db0 100644
--- a/arch/powerpc/platforms/cell/spu_base.c
+++ b/arch/powerpc/platforms/cell/spu_base.c
@@ -202,12 +202,15 @@ spu_irq_class_0(int irq, void *data, struct pt_regs *regs)
 int
 spu_irq_class_0_bottom(struct spu *spu)
 {
-	unsigned long stat;
+	unsigned long stat, mask;
 
 	spu->class_0_pending = 0;
 
+	mask = in_be64(&spu->priv1->int_mask_class0_RW);
 	stat = in_be64(&spu->priv1->int_stat_class0_RW);
 
+	stat &= mask;
+
 	if (stat & 1) /* invalid MFC DMA */
 		__spu_trap_invalid_dma(spu);
 
@@ -263,13 +266,15 @@ spu_irq_class_2(int irq, void *data, struct pt_regs *regs)
 {
 	struct spu *spu;
 	unsigned long stat;
+	unsigned long mask;
 
 	spu = data;
 	stat = in_be64(&spu->priv1->int_stat_class2_RW);
+	mask = in_be64(&spu->priv1->int_mask_class2_RW);
 
-	pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat,
-		in_be64(&spu->priv1->int_mask_class2_RW));
+	pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);
 
+	stat &= mask;
 
 	if (stat & 1)  /* PPC core mailbox */
 		__spu_trap_mailbox(spu);