diff options
| author | Lin Ming <ming.m.lin@intel.com> | 2010-03-19 15:28:58 +0800 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-03-19 09:23:17 +0100 |
| commit | 40b7e05e17eef31ff30fe08dfc2424ef653a792c (patch) | |
| tree | 915e76e0f28664707a4f41a2d75583b8dd23a9e4 /arch/x86/include/asm/perf_event_p4.h | |
| parent | 9c8c6bad3137112d2c7bf3d215b736ee4215fa74 (diff) | |
perf, x86: Fix key indexing in Pentium-4 PMU
Index 0-6 in p4_templates are reserved for common hardware
events. So p4_templates is arranged as below:
0 - 6: common hardware events
7 - N: cache events
N+1 - ...: other raw events
Reported-by: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Acked-by: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Peter Zijlstra <peterz@infradead.org>
LKML-Reference: <1268983738.13901.142.camel@minggr.sh.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/perf_event_p4.h')
| -rw-r--r-- | arch/x86/include/asm/perf_event_p4.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h index 2a1a57f71539..facf96186b26 100644 --- a/arch/x86/include/asm/perf_event_p4.h +++ b/arch/x86/include/asm/perf_event_p4.h @@ -709,7 +709,7 @@ enum P4_EVENTS_ATTR { }; enum { - KEY_P4_L1D_OP_READ_RESULT_MISS, + KEY_P4_L1D_OP_READ_RESULT_MISS = PERF_COUNT_HW_MAX, KEY_P4_LL_OP_READ_RESULT_MISS, KEY_P4_DTLB_OP_READ_RESULT_MISS, KEY_P4_DTLB_OP_WRITE_RESULT_MISS, |