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authorStefan Agner <stefan.agner@toradex.com>2019-08-16 16:40:08 +0200
committerStefan Agner <stefan.agner@toradex.com>2019-08-16 16:40:08 +0200
commit3758b8bd81966b63dc93093a323e9bdd734545fd (patch)
tree229bda2abe1a31d59da4b48e71aeefde934fe1d0 /arch/x86/kernel/cpu/bugs.c
parentd15d0b7a9f89cf5a905ad6802eb23100c8063939 (diff)
parentdd209b062b86dd951cf1da93f20aa497fe99d52d (diff)
Merge tag 'v4.19.59-rt24' into toradex_4.19.y-rttoradex_4.19.y-rt
Linux 4.19.59-rt24
Diffstat (limited to 'arch/x86/kernel/cpu/bugs.c')
-rw-r--r--arch/x86/kernel/cpu/bugs.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 9b096f26d1c8..a5cde748cf76 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -821,6 +821,16 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
}
/*
+ * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
+ * bit in the mask to allow guests to use the mitigation even in the
+ * case where the host does not enable it.
+ */
+ if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
+ static_cpu_has(X86_FEATURE_AMD_SSBD)) {
+ x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
+ }
+
+ /*
* We have three CPU feature flags that are in play here:
* - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
* - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
@@ -837,7 +847,6 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
x86_amd_ssb_disable();
} else {
x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
- x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
}
}