diff options
| author | Jim Mattson <jmattson@google.com> | 2016-11-09 09:50:11 -0800 |
|---|---|---|
| committer | Radim Krčmář <rkrcmar@redhat.com> | 2016-11-22 14:51:55 +0100 |
| commit | c7dd15b33707e99c2b66da44a2a280638b4cd14f (patch) | |
| tree | d6cc45d3e106def8da15697955e3a5cd98ccfc83 /arch/x86/kvm/cpuid.c | |
| parent | 4504b5c9414c55da37f26b1faf49c09a2acbf255 (diff) | |
kvm: x86: CPUID.01H:EDX.APIC[bit 9] should mirror IA32_APIC_BASE[11]
From the Intel SDM, volume 3, section 10.4.3, "Enabling or Disabling the
Local APIC,"
When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent
to an IA-32 processor without an on-chip APIC. The CPUID feature flag
for the APIC (see Section 10.4.2, "Presence of the Local APIC") is
also set to 0.
Signed-off-by: Jim Mattson <jmattson@google.com>
[Changed subject tag from nVMX to x86.]
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Diffstat (limited to 'arch/x86/kvm/cpuid.c')
| -rw-r--r-- | arch/x86/kvm/cpuid.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index a982fd80bceb..25f0f15fab1a 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -87,6 +87,10 @@ int kvm_update_cpuid(struct kvm_vcpu *vcpu) best->ecx |= F(OSXSAVE); } + best->edx &= ~F(APIC); + if (vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE) + best->edx |= F(APIC); + if (apic) { if (best->ecx & F(TSC_DEADLINE_TIMER)) apic->lapic_timer.timer_mode_mask = 3 << 17; |