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authorSebastian Andrzej Siewior <bigeasy@linutronix.de>2011-04-27 16:30:52 +0200
committerThomas Gleixner <tglx@linutronix.de>2011-04-28 11:38:30 +0200
commit1ff42c32c7614c2e810ed388fd1ba04a5626b74c (patch)
tree7e925c1039d35e0aea6d49b67e4c6a00ca41e0cd /arch/x86/platform
parent20443598d9bdfe3563f901e27fd482a3f5d3d231 (diff)
x86: ce4100: Configure IOAPIC pins for USB and SATA to level type
The USB and SATA ioapic interrrupt pins are configured as edge type, but need to be level type interrupts to work correctly. [ tglx: Split out from the combo patch ] Cc: Torben Hohn <torbenh@linutronix.de> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Link: http://lkml.kernel.org/r/%3C20110427143052.GA15211%40linutronix.de%3E Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/platform')
-rw-r--r--arch/x86/platform/ce4100/falconfalls.dts6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/platform/ce4100/falconfalls.dts b/arch/x86/platform/ce4100/falconfalls.dts
index 2d6d226f2b10..e70be38ce039 100644
--- a/arch/x86/platform/ce4100/falconfalls.dts
+++ b/arch/x86/platform/ce4100/falconfalls.dts
@@ -347,7 +347,7 @@
"pciclass0c03";
reg = <0x16800 0x0 0x0 0x0 0x0>;
- interrupts = <22 3>;
+ interrupts = <22 1>;
};
usb@d,1 {
@@ -357,7 +357,7 @@
"pciclass0c03";
reg = <0x16900 0x0 0x0 0x0 0x0>;
- interrupts = <22 3>;
+ interrupts = <22 1>;
};
sata@e,0 {
@@ -367,7 +367,7 @@
"pciclass0106";
reg = <0x17000 0x0 0x0 0x0 0x0>;
- interrupts = <23 3>;
+ interrupts = <23 1>;
};
flash@f,0 {