diff options
| author | Anson Huang <b20788@freescale.com> | 2015-04-09 12:54:08 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2015-05-08 17:24:47 +0800 |
| commit | a9c6755750b79f88732a3b2f5aec9983c51d541a (patch) | |
| tree | f17b86040a4bd40c8be165cac94e966296262a15 /arch | |
| parent | 241ae3a6b7672109c225b7196341106e08f5e1f7 (diff) | |
MLK-10606 ARM: imx: turn off l2pge on imx7d's dsm
As we have to flush L2 cache before entering DSM
on i.MX7D whose L2 controller is integrated into
ARM core, so we can disable L2 PGE along with SCU
to save power, it can save ~0.5mW on VDDARM, and
we can even power down VDDARM during DSM now.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/gpcv2.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c index 7c4691eed110..a3ded6cb7dcd 100644 --- a/arch/arm/mach-imx/gpcv2.c +++ b/arch/arm/mach-imx/gpcv2.c @@ -40,6 +40,7 @@ #define GPC_PU_PGC_SW_PDN_REQ 0x104 #define GPC_GTOR 0x124 #define GPC_PGC_C0 0x800 +#define GPC_PGC_SCU_TIMING 0x890 #define GPC_PGC_C1 0x840 #define GPC_PGC_SCU 0x880 #define GPC_PGC_FM 0xa00 @@ -62,6 +63,7 @@ #define BM_SLPCR_SBYOS 0x2 #define BM_SLPCR_BYPASS_PMIC_READY 0x1 +#define BM_LPCR_A7_AD_L2PGE 0x10000 #define BM_LPCR_A7_AD_EN_C1_PUP 0x800 #define BM_LPCR_A7_AD_EN_C1_IRQ_PUP 0x400 #define BM_LPCR_A7_AD_EN_C0_PUP 0x200 @@ -205,9 +207,9 @@ void imx_gpcv2_set_plat_power_gate_by_lpm(bool pdn) { u32 val = readl_relaxed(gpc_base + GPC_LPCR_A7_AD); - val &= ~BM_LPCR_A7_AD_EN_PLAT_PDN; + val &= ~(BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE); if (pdn) - val |= BM_LPCR_A7_AD_EN_PLAT_PDN; + val |= BM_LPCR_A7_AD_EN_PLAT_PDN | BM_LPCR_A7_AD_L2PGE; writel_relaxed(val, gpc_base + GPC_LPCR_A7_AD); } @@ -519,6 +521,9 @@ void __init imx_gpcv2_init(void) BM_LPCR_M4_MASK_DSM_TRIGGER, gpc_base + GPC_LPCR_M4); /* set mega/fast mix in A7 domain */ writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_MAPPING); + /* set SCU timing */ + writel_relaxed((0x59 << 10) | 0x5B | (0x51 << 20), + gpc_base + GPC_PGC_SCU_TIMING); /* Register GPC as the secondary interrupt controller behind GIC */ gic_arch_extn.irq_mask = imx_gpcv2_irq_mask; |