diff options
| author | Gary King <GKing@nvidia.com> | 2010-02-03 11:58:54 -0800 |
|---|---|---|
| committer | Gerrit Code Review <gerrit2@git-master-01.nvidia.com> | 2010-02-03 11:58:54 -0800 |
| commit | 9671c5019de83722293cee2b9459e09877f4cbd2 (patch) | |
| tree | b9088f26854dcf678db92ce0bfe5f9720856ab01 /arch | |
| parent | 693ccad4b7103f9969273d998098a7e782b74b01 (diff) | |
| parent | 303fed39d5e6b41d734a3db712106038105614d9 (diff) | |
Merge "tegra power: Add save/restore routines for warmboot registers." into android-tegra-2.6.29
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/idle-t2.c | 103 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/include/ap20/nvboot_pmc_scratch_map.h | 808 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/power-context-t2.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/power-t2.c | 281 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/power.h | 369 |
5 files changed, 1553 insertions, 12 deletions
diff --git a/arch/arm/mach-tegra/idle-t2.c b/arch/arm/mach-tegra/idle-t2.c index 1d8b5a07673a..0f3958d90f8d 100644 --- a/arch/arm/mach-tegra/idle-t2.c +++ b/arch/arm/mach-tegra/idle-t2.c @@ -28,6 +28,8 @@ #include "ap20/arflow_ctlr.h" #include "nvrm_hardware_access.h" #include "nvrm_power_private.h" +#include "nvbootargs.h" +#include "nvrm_memmgr.h" #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/wakelock.h> @@ -38,7 +40,8 @@ extern void resume(unsigned int state); extern uintptr_t g_resume, g_contextSavePA, g_contextSaveVA; extern NvU32 g_NumActiveCPUs, g_ArmPerif; extern NvU32 g_enterLP2PA; - +extern volatile void *g_pPMC, *g_pAHB, *g_pCLK_RST_CONTROLLER; +extern volatile void *g_pEMC, *g_pMC, *g_pAPB_MISC; #ifdef CONFIG_WAKELOCK extern struct wake_lock main_wake_lock; #endif @@ -62,7 +65,10 @@ void mach_tegra_idle(void); extern void enter_lp2(NvU32, NvU32); extern void exit_power_state(void); extern void module_context_init(void); +extern void power_lp0_init(void); extern void NvSpareTimerTrigger(unsigned long); /* timer.c */ +NvRmMemHandle s_hWarmboot = NULL; +NvU32 g_AvpWarmbootEntry; NvU32 lp2count = 0, lp3count = 0, lp2safe = 0; @@ -73,15 +79,16 @@ void __init NvAp20InitFlowController(void) NvU32 len; NvRmPhysAddr pa; volatile NvU8 *pTempFc, *pTempArmPerif; - + NvBootArgsWarmboot WarmbootArgs; + NvRmModuleGetBaseAddress(s_hRmGlobal, NVRM_MODULE_ID(NvRmModuleID_FlowCtrl, 0), &pa, &len); if (NvRmPhysicalMemMap(pa, len, NVOS_MEM_READ_WRITE, NvOsMemAttribute_Uncached, (void**)&pTempFc)!=NvSuccess) { - printk(KERN_INFO "failed to map flow controller; DVFS will not function" - " correctly as a result\n"); + printk(KERN_INFO "failed to map flow controller; " + " DVFS will not function correctly as a result\n"); return; } @@ -96,6 +103,77 @@ void __init NvAp20InitFlowController(void) return; } + NvRmModuleGetBaseAddress(s_hRmGlobal, + NVRM_MODULE_ID(NvRmModuleID_Pmif, 0), &pa, &len); + + if (NvRmPhysicalMemMap(pa, len, NVOS_MEM_READ_WRITE, + NvOsMemAttribute_Uncached, (void**)&g_pPMC)!=NvSuccess) + { + printk(KERN_INFO "failed to map pmif; DVFS will not function" + " correctly as a result\n"); + return; + } + + NvRmModuleGetBaseAddress(s_hRmGlobal, + NVRM_MODULE_ID(NvRmPrivModuleID_Ahb_Arb_Ctrl, 0), &pa, &len); + + if (NvRmPhysicalMemMap(pa, len, NVOS_MEM_READ_WRITE, + NvOsMemAttribute_Uncached, (void**)&g_pAHB)!=NvSuccess) + { + printk(KERN_INFO "failed to map ahb; DVFS will not function" + " correctly as a result\n"); + return; + } + + NvRmModuleGetBaseAddress(s_hRmGlobal, + NVRM_MODULE_ID(NvRmPrivModuleID_ClockAndReset, 0), &pa, &len); + + if (NvRmPhysicalMemMap(pa, len, NVOS_MEM_READ_WRITE, + NvOsMemAttribute_Uncached, + (void**)&g_pCLK_RST_CONTROLLER)!=NvSuccess) + { + printk(KERN_INFO "failed to map car; DVFS will not function" + " correctly as a result\n"); + return; + } + + NvRmModuleGetBaseAddress(s_hRmGlobal, + NVRM_MODULE_ID(NvRmPrivModuleID_ExternalMemoryController, 0), + &pa, &len); + + if (NvRmPhysicalMemMap(pa, len, NVOS_MEM_READ_WRITE, + NvOsMemAttribute_Uncached, + (void**)&g_pEMC)!=NvSuccess) + { + printk(KERN_INFO "failed to map emc; DVFS will not function" + " correctly as a result\n"); + return; + } + + NvRmModuleGetBaseAddress(s_hRmGlobal, + NVRM_MODULE_ID(NvRmPrivModuleID_MemoryController, 0), &pa, &len); + + if (NvRmPhysicalMemMap(pa, len, NVOS_MEM_READ_WRITE, + NvOsMemAttribute_Uncached, + (void**)&g_pMC)!=NvSuccess) + { + printk(KERN_INFO "failed to map mc; DVFS will not function" + " correctly as a result\n"); + return; + } + + NvRmModuleGetBaseAddress(s_hRmGlobal, + NVRM_MODULE_ID(NvRmModuleID_Misc, 0), &pa, &len); + + if (NvRmPhysicalMemMap(pa, len, NVOS_MEM_READ_WRITE, + NvOsMemAttribute_Uncached, + (void**)&g_pAPB_MISC)!=NvSuccess) + { + printk(KERN_INFO "failed to map misc; DVFS will not function" + " correctly as a result\n"); + return; + } + s_pFlowCtrl = pTempFc; g_ArmPerif = (NvU32)pTempArmPerif; @@ -110,8 +188,22 @@ void __init NvAp20InitFlowController(void) g_contextSavePA = virt_to_phys((void*)g_contextSaveVA); g_NumActiveCPUs = num_online_cpus(); g_enterLP2PA = virt_to_phys((void*)enter_lp2); + + NvOsBootArgGet(NvBootArgKey_WarmBoot, + &WarmbootArgs, sizeof(NvBootArgsWarmboot)); + if (NvRmMemHandleClaimPreservedHandle(s_hRmGlobal, + WarmbootArgs.MemHandleKey, &s_hWarmboot)) + { + printk("Could not locate Warm booloader!\n"); + } + else + { + g_AvpWarmbootEntry = NvRmMemPin(s_hWarmboot); + } + #if ENABLE_LP0 - module_context_init(); + module_context_init(); + power_lp0_init(); #endif } @@ -169,7 +261,6 @@ void mach_tegra_idle(void) static NvU64 cur_jiffies = 0, old_jiffies = 0; NvU64 delta_jif = 0; NvU32 msec, delta; - NvRmDfsClockUsage clock_usage; #ifdef CONFIG_WAKELOCK //The wake lock api is ready if the main lock is ready diff --git a/arch/arm/mach-tegra/include/ap20/nvboot_pmc_scratch_map.h b/arch/arm/mach-tegra/include/ap20/nvboot_pmc_scratch_map.h index 8a2a44d1b68a..7f687a75b0b0 100644 --- a/arch/arm/mach-tegra/include/ap20/nvboot_pmc_scratch_map.h +++ b/arch/arm/mach-tegra/include/ap20/nvboot_pmc_scratch_map.h @@ -37,8 +37,816 @@ #ifndef INCLUDED_NVBOOT_PMC_SCRATCH_MAP_H #define INCLUDED_NVBOOT_PMC_SCRATCH_MAP_H +// Special definition for the subset of EMC_FBIO_SPARE restored in WB0. +#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_RANGE 31:24 +#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_SHIFT _MK_SHIFT_CONST(24) +#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + #define APBDEV_PMC_SCRATCH0_0_WARM_BOOT0_FLAG_RANGE 0:0 #define APBDEV_PMC_SCRATCH0_0_WARM_BOOT0_FLAG_SHIFT _MK_SHIFT_CONST(0) #define APBDEV_PMC_SCRATCH0_0_WARM_BOOT0_FLAG_DEFAULT_MASK _MK_MASK_CONST(0x00000001) +/** + * MEMORY_TYPE: + * Source: SDRAM[n].MemoryType + * Desc: An enumerated constant that identifies the type of SDRAM + * (DDR, DDR2, LPDDR, LPDDR2), as the initialization sequence is different + * for each of them. DDR is only valid for FPGA emulation, but the + * Boot ROM code does not make this distinction. + */ +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVM_RANGE 4:0 +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVM_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVM_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVN_RANGE 14:5 +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVN_SHIFT _MK_SHIFT_CONST(5) +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVN_DEFAULT_MASK _MK_MASK_CONST(0x000003FF) + +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVP_RANGE 17:15 +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVP_SHIFT _MK_SHIFT_CONST(15) +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVP_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_LFCON_RANGE 21:18 +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_LFCON_SHIFT _MK_SHIFT_CONST(18) +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_LFCON_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_CPCON_RANGE 25:22 +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_CPCON_SHIFT _MK_SHIFT_CONST(22) +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_CPCON_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_RANGE 26:26 +#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SHIFT _MK_SHIFT_CONST(26) +#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_RANGE 27:27 +#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT _MK_SHIFT_CONST(27) +#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_OSC_CTRL_XOBP_RANGE 28:28 +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_OSC_CTRL_XOBP_SHIFT _MK_SHIFT_CONST(28) +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_OSC_CTRL_XOBP_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH2_0_MEMORY_TYPE_RANGE 31:29 +#define APBDEV_PMC_SCRATCH2_0_MEMORY_TYPE_SHIFT _MK_SHIFT_CONST(29) +#define APBDEV_PMC_SCRATCH2_0_MEMORY_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + + +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVM_RANGE 4:0 +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVM_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVM_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVN_RANGE 14:5 +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVN_SHIFT _MK_SHIFT_CONST(5) +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVN_DEFAULT_MASK _MK_MASK_CONST(0x000003FF) + +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVP_RANGE 17:15 +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVP_SHIFT _MK_SHIFT_CONST(15) +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVP_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_LFCON_RANGE 21:18 +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_LFCON_SHIFT _MK_SHIFT_CONST(18) +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_LFCON_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_CPCON_RANGE 25:22 +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_CPCON_SHIFT _MK_SHIFT_CONST(22) +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_CPCON_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_RANGE 26:26 +#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT _MK_SHIFT_CONST(26) +#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_RANGE 30:27 +#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SHIFT _MK_SHIFT_CONST(27) +#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_RANGE 31:31 +#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SHIFT _MK_SHIFT_CONST(31) +#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + + +/** + * PLLM_STABLE_TIME: + * Source: SDRAM[n].PllMStableTime + * Dest: SDRAM initialization code + * Desc: Time to wait for PLLM to become stable, in microseconds. Overrides + * internal stabilization time values. + * PLLX_STABLE_TIME: + * Source: SDRAM[n].PllXStableTime + * Dest: PLLX initialization code for WB0 + * Desc: Time to wait for PLLM to become stable, in microseconds. Overrides + * internal stabilization time values. + * EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0: + * Source: SDRAM[n].EmcFbioSpare (upper 8 bits) + * Dest: Upper 8 bits of EMC_FBIO_SPARE + * Desc: To avoid wasting all 32-bits of PMC scratch for spare bits for + * some future use, only the upper 8 bits are preserved. + */ +#define APBDEV_PMC_SCRATCH4_0_EMC_CLOCK_DIVIDER_RANGE 7:0 +#define APBDEV_PMC_SCRATCH4_0_EMC_CLOCK_DIVIDER_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH4_0_EMC_CLOCK_DIVIDER_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +#define APBDEV_PMC_SCRATCH4_0_PLLM_STABLE_TIME_RANGE 15:8 +#define APBDEV_PMC_SCRATCH4_0_PLLM_STABLE_TIME_SHIFT _MK_SHIFT_CONST(8) +#define APBDEV_PMC_SCRATCH4_0_PLLM_STABLE_TIME_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +#define APBDEV_PMC_SCRATCH4_0_PLLX_STABLE_TIME_RANGE 23:16 +#define APBDEV_PMC_SCRATCH4_0_PLLX_STABLE_TIME_SHIFT _MK_SHIFT_CONST(16) +#define APBDEV_PMC_SCRATCH4_0_PLLX_STABLE_TIME_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +#define APBDEV_PMC_SCRATCH4_0_EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_RANGE 31:24 +#define APBDEV_PMC_SCRATCH4_0_EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH4_0_EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + + +#define APBDEV_PMC_SCRATCH5_0_EMC_RC_0_RC_RANGE 5:0 +#define APBDEV_PMC_SCRATCH5_0_EMC_RC_0_RC_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH5_0_EMC_RC_0_RC_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH5_0_EMC_RFC_0_RFC_RANGE 14:6 +#define APBDEV_PMC_SCRATCH5_0_EMC_RFC_0_RFC_SHIFT _MK_SHIFT_CONST(6) +#define APBDEV_PMC_SCRATCH5_0_EMC_RFC_0_RFC_DEFAULT_MASK _MK_MASK_CONST(0x000001FF) + +#define APBDEV_PMC_SCRATCH5_0_EMC_RAS_0_RAS_RANGE 20:15 +#define APBDEV_PMC_SCRATCH5_0_EMC_RAS_0_RAS_SHIFT _MK_SHIFT_CONST(15) +#define APBDEV_PMC_SCRATCH5_0_EMC_RAS_0_RAS_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH5_0_EMC_RP_0_RP_RANGE 26:21 +#define APBDEV_PMC_SCRATCH5_0_EMC_RP_0_RP_SHIFT _MK_SHIFT_CONST(21) +#define APBDEV_PMC_SCRATCH5_0_EMC_RP_0_RP_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH5_0_EMC_R2W_0_R2W_RANGE 31:27 +#define APBDEV_PMC_SCRATCH5_0_EMC_R2W_0_R2W_SHIFT _MK_SHIFT_CONST(27) +#define APBDEV_PMC_SCRATCH5_0_EMC_R2W_0_R2W_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + + +#define APBDEV_PMC_SCRATCH6_0_EMC_W2R_0_W2R_RANGE 4:0 +#define APBDEV_PMC_SCRATCH6_0_EMC_W2R_0_W2R_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH6_0_EMC_W2R_0_W2R_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH6_0_EMC_R2P_0_R2P_RANGE 9:5 +#define APBDEV_PMC_SCRATCH6_0_EMC_R2P_0_R2P_SHIFT _MK_SHIFT_CONST(5) +#define APBDEV_PMC_SCRATCH6_0_EMC_R2P_0_R2P_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH6_0_EMC_W2P_0_W2P_RANGE 14:10 +#define APBDEV_PMC_SCRATCH6_0_EMC_W2P_0_W2P_SHIFT _MK_SHIFT_CONST(10) +#define APBDEV_PMC_SCRATCH6_0_EMC_W2P_0_W2P_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH6_0_EMC_RD_RCD_0_RD_RCD_RANGE 20:15 +#define APBDEV_PMC_SCRATCH6_0_EMC_RD_RCD_0_RD_RCD_SHIFT _MK_SHIFT_CONST(15) +#define APBDEV_PMC_SCRATCH6_0_EMC_RD_RCD_0_RD_RCD_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH6_0_EMC_WR_RCD_0_WR_RCD_RANGE 26:21 +#define APBDEV_PMC_SCRATCH6_0_EMC_WR_RCD_0_WR_RCD_SHIFT _MK_SHIFT_CONST(21) +#define APBDEV_PMC_SCRATCH6_0_EMC_WR_RCD_0_WR_RCD_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH6_0_EMC_RRD_0_RRD_RANGE 30:27 +#define APBDEV_PMC_SCRATCH6_0_EMC_RRD_0_RRD_SHIFT _MK_SHIFT_CONST(27) +#define APBDEV_PMC_SCRATCH6_0_EMC_RRD_0_RRD_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + + +#define APBDEV_PMC_SCRATCH7_0_EMC_REXT_0_REXT_RANGE 3:0 +#define APBDEV_PMC_SCRATCH7_0_EMC_REXT_0_REXT_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH7_0_EMC_REXT_0_REXT_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH7_0_EMC_WDV_0_WDV_RANGE 7:4 +#define APBDEV_PMC_SCRATCH7_0_EMC_WDV_0_WDV_SHIFT _MK_SHIFT_CONST(4) +#define APBDEV_PMC_SCRATCH7_0_EMC_WDV_0_WDV_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH7_0_EMC_QUSE_0_QUSE_RANGE 11:8 +#define APBDEV_PMC_SCRATCH7_0_EMC_QUSE_0_QUSE_SHIFT _MK_SHIFT_CONST(8) +#define APBDEV_PMC_SCRATCH7_0_EMC_QUSE_0_QUSE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH7_0_EMC_QRST_0_QRST_RANGE 15:12 +#define APBDEV_PMC_SCRATCH7_0_EMC_QRST_0_QRST_SHIFT _MK_SHIFT_CONST(12) +#define APBDEV_PMC_SCRATCH7_0_EMC_QRST_0_QRST_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH7_0_EMC_QSAFE_0_QSAFE_RANGE 19:16 +#define APBDEV_PMC_SCRATCH7_0_EMC_QSAFE_0_QSAFE_SHIFT _MK_SHIFT_CONST(16) +#define APBDEV_PMC_SCRATCH7_0_EMC_QSAFE_0_QSAFE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH7_0_EMC_RDV_0_RDV_RANGE 24:20 +#define APBDEV_PMC_SCRATCH7_0_EMC_RDV_0_RDV_SHIFT _MK_SHIFT_CONST(20) +#define APBDEV_PMC_SCRATCH7_0_EMC_RDV_0_RDV_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH7_0_EMC_PCHG2PDEN_0_PCHG2PDEN_RANGE 29:25 +#define APBDEV_PMC_SCRATCH7_0_EMC_PCHG2PDEN_0_PCHG2PDEN_SHIFT _MK_SHIFT_CONST(25) +#define APBDEV_PMC_SCRATCH7_0_EMC_PCHG2PDEN_0_PCHG2PDEN_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_USE_ADDR_CLK_RANGE 30:30 +#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_USE_ADDR_CLK_SHIFT _MK_SHIFT_CONST(30) +#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_USE_ADDR_CLK_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_RANGE 31:31 +#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_SHIFT _MK_SHIFT_CONST(31) +#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + + +#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_LO_RANGE 4:0 +#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_LO_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_LO_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_RANGE 15:5 +#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_SHIFT _MK_SHIFT_CONST(5) +#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_DEFAULT_MASK _MK_MASK_CONST(0x000007FF) + +#define APBDEV_PMC_SCRATCH8_0_EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_RANGE 19:16 +#define APBDEV_PMC_SCRATCH8_0_EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_SHIFT _MK_SHIFT_CONST(16) +#define APBDEV_PMC_SCRATCH8_0_EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2WR_0_PDEX2WR_RANGE 23:20 +#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2WR_0_PDEX2WR_SHIFT _MK_SHIFT_CONST(20) +#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2WR_0_PDEX2WR_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2RD_0_PDEX2RD_RANGE 27:24 +#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2RD_0_PDEX2RD_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2RD_0_PDEX2RD_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH8_0_EMC_TCLKSTABLE_0_TCLKSTABLE_RANGE 31:28 +#define APBDEV_PMC_SCRATCH8_0_EMC_TCLKSTABLE_0_TCLKSTABLE_SHIFT _MK_SHIFT_CONST(28) +#define APBDEV_PMC_SCRATCH8_0_EMC_TCLKSTABLE_0_TCLKSTABLE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + + +#define APBDEV_PMC_SCRATCH9_0_EMC_ACT2PDEN_0_ACT2PDEN_RANGE 4:0 +#define APBDEV_PMC_SCRATCH9_0_EMC_ACT2PDEN_0_ACT2PDEN_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH9_0_EMC_ACT2PDEN_0_ACT2PDEN_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH9_0_EMC_AR2PDEN_0_AR2PDEN_RANGE 9:5 +#define APBDEV_PMC_SCRATCH9_0_EMC_AR2PDEN_0_AR2PDEN_SHIFT _MK_SHIFT_CONST(5) +#define APBDEV_PMC_SCRATCH9_0_EMC_AR2PDEN_0_AR2PDEN_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH9_0_EMC_RW2PDEN_0_RW2PDEN_RANGE 15:10 +#define APBDEV_PMC_SCRATCH9_0_EMC_RW2PDEN_0_RW2PDEN_SHIFT _MK_SHIFT_CONST(10) +#define APBDEV_PMC_SCRATCH9_0_EMC_RW2PDEN_0_RW2PDEN_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH9_0_EMC_TXSR_0_TXSR_RANGE 27:16 +#define APBDEV_PMC_SCRATCH9_0_EMC_TXSR_0_TXSR_SHIFT _MK_SHIFT_CONST(16) +#define APBDEV_PMC_SCRATCH9_0_EMC_TXSR_0_TXSR_DEFAULT_MASK _MK_MASK_CONST(0x00000FFF) + +#define APBDEV_PMC_SCRATCH9_0_EMC_TCKE_0_TCKE_RANGE 31:28 +#define APBDEV_PMC_SCRATCH9_0_EMC_TCKE_0_TCKE_SHIFT _MK_SHIFT_CONST(28) +#define APBDEV_PMC_SCRATCH9_0_EMC_TCKE_0_TCKE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + + +#define APBDEV_PMC_SCRATCH10_0_EMC_TRPAB_0_TRPAB_RANGE 5:0 +#define APBDEV_PMC_SCRATCH10_0_EMC_TRPAB_0_TRPAB_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH10_0_EMC_TRPAB_0_TRPAB_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH10_0_EMC_TCLKSTOP_0_TCLKSTOP_RANGE 9:6 +#define APBDEV_PMC_SCRATCH10_0_EMC_TCLKSTOP_0_TCLKSTOP_SHIFT _MK_SHIFT_CONST(6) +#define APBDEV_PMC_SCRATCH10_0_EMC_TCLKSTOP_0_TCLKSTOP_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH10_0_EMC_TREFBW_0_TREFBW_RANGE 23:10 +#define APBDEV_PMC_SCRATCH10_0_EMC_TREFBW_0_TREFBW_SHIFT _MK_SHIFT_CONST(10) +#define APBDEV_PMC_SCRATCH10_0_EMC_TREFBW_0_TREFBW_DEFAULT_MASK _MK_MASK_CONST(0x00003FFF) + +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_MUX_RANGE 24:24 +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_MUX_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_MUX_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_WRITE_MUX_RANGE 25:25 +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_WRITE_MUX_SHIFT _MK_SHIFT_CONST(25) +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_WRITE_MUX_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_FORCE_UPDATE_RANGE 26:26 +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_FORCE_UPDATE_SHIFT _MK_SHIFT_CONST(26) +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_FORCE_UPDATE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_MRS_WAIT_RANGE 27:27 +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_MRS_WAIT_SHIFT _MK_SHIFT_CONST(27) +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_MRS_WAIT_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_PERIODIC_QRST_RANGE 28:28 +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_PERIODIC_QRST_SHIFT _MK_SHIFT_CONST(28) +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_PERIODIC_QRST_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_DQM_CTRL_RANGE 29:29 +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_DQM_CTRL_SHIFT _MK_SHIFT_CONST(29) +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_DQM_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_AP_REQ_BUSY_CTRL_RANGE 30:30 +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_AP_REQ_BUSY_CTRL_SHIFT _MK_SHIFT_CONST(30) +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_AP_REQ_BUSY_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_CFG_PRIORITY_RANGE 31:31 +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_CFG_PRIORITY_SHIFT _MK_SHIFT_CONST(31) +#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_CFG_PRIORITY_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + + +// Note: 1 bit is reserved. +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_RANGE 1:0 +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_RANGE 3:2 +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_SHIFT _MK_SHIFT_CONST(2) +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_RANGE 5:4 +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_SHIFT _MK_SHIFT_CONST(4) +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_RANGE 7:6 +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_SHIFT _MK_SHIFT_CONST(6) +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_RANGE 9:8 +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_SHIFT _MK_SHIFT_CONST(8) +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_RANGE 11:10 +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_SHIFT _MK_SHIFT_CONST(10) +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_RANGE 13:12 +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_SHIFT _MK_SHIFT_CONST(12) +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_RANGE 15:14 +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_SHIFT _MK_SHIFT_CONST(14) +#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH11_0_EMC_TFAW_0_TFAW_RANGE 21:16 +#define APBDEV_PMC_SCRATCH11_0_EMC_TFAW_0_TFAW_SHIFT _MK_SHIFT_CONST(16) +#define APBDEV_PMC_SCRATCH11_0_EMC_TFAW_0_TFAW_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH11_0_EMC_QUSE_EXTRA_0_QUSE_EXTRA_RANGE 25:22 +#define APBDEV_PMC_SCRATCH11_0_EMC_QUSE_EXTRA_0_QUSE_EXTRA_SHIFT _MK_SHIFT_CONST(22) +#define APBDEV_PMC_SCRATCH11_0_EMC_QUSE_EXTRA_0_QUSE_EXTRA_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_RANGE 29:26 +#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SHIFT _MK_SHIFT_CONST(26) +#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_RANGE 30:30 +#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SHIFT _MK_SHIFT_CONST(30) +#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + + +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_RANGE 7:0 +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_RANGE 15:8 +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SHIFT _MK_SHIFT_CONST(8) +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_RANGE 23:16 +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SHIFT _MK_SHIFT_CONST(16) +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_RANGE 31:24 +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + + +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_RANGE 7:0 +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_RANGE 15:8 +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SHIFT _MK_SHIFT_CONST(8) +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_RANGE 23:16 +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SHIFT _MK_SHIFT_CONST(16) +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_RANGE 31:24 +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + + +// Note: 2 bits are reserved. +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_RANGE 5:0 +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_RANGE 11:6 +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_SHIFT _MK_SHIFT_CONST(6) +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_RANGE 17:12 +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_SHIFT _MK_SHIFT_CONST(12) +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_RANGE 23:18 +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_SHIFT _MK_SHIFT_CONST(18) +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_RANGE 29:24 +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + + +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG1_0_CFG_DEN_EARLY_RANGE 0:0 +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG6_0_CFG_QUSE_LATE_RANGE 3:1 +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SHIFT _MK_SHIFT_CONST(1) +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG6_0_CFG_QUSE_LATE_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_TYPE_RANGE 5:4 +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_TYPE_SHIFT _MK_SHIFT_CONST(4) +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_WIDTH_RANGE 6:6 +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_WIDTH_SHIFT _MK_SHIFT_CONST(6) +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_WIDTH_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_RANGE 7:7 +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_SHIFT _MK_SHIFT_CONST(7) +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_CTT_TERMINATION_RANGE 8:8 +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_CTT_TERMINATION_SHIFT _MK_SHIFT_CONST(8) +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_CTT_TERMINATION_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_RANGE 13:9 +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT _MK_SHIFT_CONST(9) +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_RANGE 18:14 +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT _MK_SHIFT_CONST(14) +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_RANGE 28:19 +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT _MK_SHIFT_CONST(19) +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT_MASK _MK_MASK_CONST(0x000003FF) + +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_RANGE 29:29 +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SHIFT _MK_SHIFT_CONST(29) +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_RANGE 30:30 +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT _MK_SHIFT_CONST(30) +#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DQS_PULLD_RANGE 31:31 +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DQS_PULLD_SHIFT _MK_SHIFT_CONST(31) +#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DQS_PULLD_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + + +#define APBDEV_PMC_SCRATCH16_0_EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_RANGE 27:0 +#define APBDEV_PMC_SCRATCH16_0_EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH16_0_EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT_MASK _MK_MASK_CONST(0x0FFFFFFF) + +#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_RANGE 28:28 +#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_SHIFT _MK_SHIFT_CONST(28) +#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_RANGE 29:29 +#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_SHIFT _MK_SHIFT_CONST(29) +#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_PIN_CONFIG_RANGE 31:30 +#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_PIN_CONFIG_SHIFT _MK_SHIFT_CONST(30) +#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_PIN_CONFIG_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + + +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_COLWIDTH_RANGE 2:0 +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_COLWIDTH_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_BANKWIDTH_RANGE 4:3 +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT _MK_SHIFT_CONST(3) +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_DEVSIZE_RANGE 8:5 +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_DEVSIZE_SHIFT _MK_SHIFT_CONST(5) +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_NUMDEV_RANGE 10:9 +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_NUMDEV_SHIFT _MK_SHIFT_CONST(9) +#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_NUMDEV_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_EN_RANGE 11:11 +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_EN_SHIFT _MK_SHIFT_CONST(11) +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_CYCLES_RANGE 19:12 +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_CYCLES_SHIFT _MK_SHIFT_CONST(12) +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_CYCLES_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_CLEAR_AP_PREV_SPREQ_RANGE 20:20 +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SHIFT _MK_SHIFT_CONST(20) +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_RD_RANGE 21:21 +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_RD_SHIFT _MK_SHIFT_CONST(21) +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_RD_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_WR_RANGE 22:22 +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_WR_SHIFT _MK_SHIFT_CONST(22) +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_WR_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_ACPD_RANGE 23:23 +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_ACPD_SHIFT _MK_SHIFT_CONST(23) +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_ACPD_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_RANGE 24:24 +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_RANGE 25:25 +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_SHIFT _MK_SHIFT_CONST(25) +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_RANGE 26:26 +#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SHIFT _MK_SHIFT_CONST(26) +#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_RANGE 27:27 +#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SHIFT _MK_SHIFT_CONST(27) +#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_RANGE 29:28 +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_SHIFT _MK_SHIFT_CONST(28) +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RANGE 31:30 +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_SHIFT _MK_SHIFT_CONST(30) +#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + + +#define APBDEV_PMC_SCRATCH18_0_EMC_CTT_TERM_CTRL_0_TERM_DRVUP_RANGE 4:0 +#define APBDEV_PMC_SCRATCH18_0_EMC_CTT_TERM_CTRL_0_TERM_DRVUP_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH18_0_EMC_CTT_TERM_CTRL_0_TERM_DRVUP_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_RANGE 7:5 +#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_SHIFT _MK_SHIFT_CONST(5) +#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_RANGE 9:8 +#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_SHIFT _MK_SHIFT_CONST(8) +#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_DEFAULT_MASK _MK_MASK_CONST(0x00000003) + +#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_RANGE 13:10 +#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_SHIFT _MK_SHIFT_CONST(10) +#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_RANGE 17:14 +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SHIFT _MK_SHIFT_CONST(14) +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_RANGE 20:18 +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SHIFT _MK_SHIFT_CONST(18) +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_RANGE 23:21 +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SHIFT _MK_SHIFT_CONST(21) +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_RANGE 26:24 +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_RANGE 29:27 +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SHIFT _MK_SHIFT_CONST(27) +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_RANGE 30:30 +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SHIFT _MK_SHIFT_CONST(30) +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_RANGE 31:31 +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SHIFT _MK_SHIFT_CONST(31) +#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + + +#define APBDEV_PMC_SCRATCH19_0_MC_EMEM_CFG_0_EMEM_SIZE_KB_RANGE 21:0 +#define APBDEV_PMC_SCRATCH19_0_MC_EMEM_CFG_0_EMEM_SIZE_KB_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH19_0_MC_EMEM_CFG_0_EMEM_SIZE_KB_DEFAULT_MASK _MK_MASK_CONST(0x003FFFFF) + +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_EN_RANGE 22:22 +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_EN_SHIFT _MK_SHIFT_CONST(22) +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_RANGE 23:23 +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_SHIFT _MK_SHIFT_CONST(23) +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_RANGE 24:24 +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_RANGE 25:25 +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_SHIFT _MK_SHIFT_CONST(25) +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_RANGE 26:26 +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_SHIFT _MK_SHIFT_CONST(26) +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_RANGE 27:27 +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_SHIFT _MK_SHIFT_CONST(27) +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_RANGE 31:28 +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_SHIFT _MK_SHIFT_CONST(28) +#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_DEFAULT_MASK _MK_MASK_CONST(0x0000000F) + + +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_RANGE 5:0 +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_RANGE 11:6 +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_SHIFT _MK_SHIFT_CONST(6) +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_RANGE 17:12 +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_SHIFT _MK_SHIFT_CONST(12) +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_RANGE 23:18 +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_SHIFT _MK_SHIFT_CONST(18) +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_RANGE 29:24 +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_RANGE 30:30 +#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SHIFT _MK_SHIFT_CONST(30) +#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_RANGE 31:31 +#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SHIFT _MK_SHIFT_CONST(31) +#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + + +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_RANGE 5:0 +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_RANGE 11:6 +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_SHIFT _MK_SHIFT_CONST(6) +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_RANGE 17:12 +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_SHIFT _MK_SHIFT_CONST(12) +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_RANGE 23:18 +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_SHIFT _MK_SHIFT_CONST(18) +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_RANGE 29:24 +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F) + +#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_RANGE 30:30 +#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SHIFT _MK_SHIFT_CONST(30) +#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_RANGE 31:31 +#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SHIFT _MK_SHIFT_CONST(31) +#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + + +// Note: 1 bit reserved +#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_RANGE 4:0 +#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_RANGE 19:5 +#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_SHIFT _MK_SHIFT_CONST(5) +#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_DEFAULT_MASK _MK_MASK_CONST(0x00007FFF) + +#define APBDEV_PMC_SCRATCH22_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_RANGE 29:20 +#define APBDEV_PMC_SCRATCH22_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_SHIFT _MK_SHIFT_CONST(20) +#define APBDEV_PMC_SCRATCH22_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_DEFAULT_MASK _MK_MASK_CONST(0x000003FF) + +#define APBDEV_PMC_SCRATCH22_0_MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_RANGE 30:30 +#define APBDEV_PMC_SCRATCH22_0_MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SHIFT _MK_SHIFT_CONST(30) +#define APBDEV_PMC_SCRATCH22_0_MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + + +// Note: 2 bits reserved +#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_RANGE 4:0 +#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_RANGE 19:5 +#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_SHIFT _MK_SHIFT_CONST(5) +#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_DEFAULT_MASK _MK_MASK_CONST(0x00007FFF) + +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_WR_DELAY_RANGE 22:20 +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_WR_DELAY_SHIFT _MK_SHIFT_CONST(20) +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_WR_DELAY_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_B4_WRITE_RANGE 23:23 +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_B4_WRITE_SHIFT _MK_SHIFT_CONST(23) +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_B4_WRITE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_RANGE 24:24 +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_RD_DELAY_RANGE 27:25 +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_RD_DELAY_SHIFT _MK_SHIFT_CONST(25) +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_RD_DELAY_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_B4_READ_RANGE 28:28 +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_B4_READ_SHIFT _MK_SHIFT_CONST(28) +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_B4_READ_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_RANGE 29:29 +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_SHIFT _MK_SHIFT_CONST(29) +#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + + +/** + * AHB_ARBITRATION_XBAR_CTRL: + * Source: SDRAM[n].AhbArbitrationXbarCtrl + * Dest: AHB_ARBITRATION_XBAR_CTRL + * Desc: Note: Only bits 0, 1, and 16 are actually used in this scratch + * register. However, the Boot ROM copies the entire 32 bits to + * AHB_ARBITRATION_XBAR_CTRL. The 3 single-bit definitions are provided + * for convenience/reference. + */ +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_RANGE 0:0 +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_RANGE 1:1 +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SHIFT _MK_SHIFT_CONST(1) +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_RANGE 16:16 +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SHIFT _MK_SHIFT_CONST(16) +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_RANGE 31:0 +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_DEFAULT_MASK _MK_MASK_CONST(0xFFFFFFFF) + +#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_RANGE 23:0 +#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_DEFAULT_MASK _MK_MASK_CONST(0x00FFFFFF) + +#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_RANGE 31:24 +#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_SHIFT _MK_SHIFT_CONST(24) +#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + + +// Note: 2 bits are reserved. +#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_RANGE 7:0 +#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_RANGE 15:8 +#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_SHIFT _MK_SHIFT_CONST(8) +#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_DEFAULT_MASK _MK_MASK_CONST(0x000000FF) + +// bits [17:16] reserved +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_SLOPE_RANGE 20:18 +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_SLOPE_SHIFT _MK_SHIFT_CONST(18) +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_SLOPE_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OFFSET_RANGE 25:21 +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OFFSET_SHIFT _MK_SHIFT_CONST(21) +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OFFSET_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_DRVDN_RANGE 30:26 +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_DRVDN_SHIFT _MK_SHIFT_CONST(26) +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_DRVDN_DEFAULT_MASK _MK_MASK_CONST(0x0000001F) + +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_RANGE 31:31 +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_SHIFT _MK_SHIFT_CONST(31) +#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + + +// Scratch registers 37, 38, and 39 are reserved for SW. + +// The last three scratch registers are reseved for HW ECO's. +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_RANGE 2:0 +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SHIFT _MK_SHIFT_CONST(0) +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_RANGE 5:3 +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SHIFT _MK_SHIFT_CONST(3) +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_RANGE 8:6 +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SHIFT _MK_SHIFT_CONST(6) +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_RANGE 11:9 +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SHIFT _MK_SHIFT_CONST(9) +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_DEFAULT_MASK _MK_MASK_CONST(0x00000007) + +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_RANGE 12:12 +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SHIFT _MK_SHIFT_CONST(12) +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_RANGE 13:13 +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SHIFT _MK_SHIFT_CONST(13) +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_RANGE 14:14 +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SHIFT _MK_SHIFT_CONST(14) +#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001) + #endif // INCLUDED_NVBOOT_APBDEV_PMC_SCRATCH_MAP_H diff --git a/arch/arm/mach-tegra/power-context-t2.c b/arch/arm/mach-tegra/power-context-t2.c index e4f982acfabd..70e21f1237d4 100644 --- a/arch/arm/mach-tegra/power-context-t2.c +++ b/arch/arm/mach-tegra/power-context-t2.c @@ -46,6 +46,7 @@ NvU32* perform_context_operation(PowerModuleContext Context); void prepare_for_wb0(void); struct power_context *s_pModulesContextAnchor = NULL; +extern NvU32 g_AvpWarmbootEntry; #define WORKAROUND_573705 1 #define MODULE_CONTEXT_SAVE_AREA_SIZE 4096 @@ -62,7 +63,8 @@ static void update_registers_for_lp0(void) APBDEV_PMC_SCRATCH0_0, Reg); //SCRATCH1 : AVP-side recovery physical address. - //FIXME: Need to get the AVP restore address from the bootloader + NV_REGW(s_hRmGlobal, NvRmModuleID_Pmif, 0, + APBDEV_PMC_SCRATCH1_0, g_AvpWarmbootEntry); //SCRATCH41 : CPU-side recovery physical address. //LP0 needs the resume address in SCRATCH41 diff --git a/arch/arm/mach-tegra/power-t2.c b/arch/arm/mach-tegra/power-t2.c index f4c05718d05b..25bee44d12a3 100644 --- a/arch/arm/mach-tegra/power-t2.c +++ b/arch/arm/mach-tegra/power-t2.c @@ -35,6 +35,12 @@ void enable_pll(PowerPll pll, NvBool enable); void enable_plls(NvBool enable); void do_suspend_prep(void); void reset_cpu(unsigned int cpu, unsigned int reset); +static void init_lp0_scratch_registers(void); +static void create_wakeup_irqs(void); +void shadow_runstate_scratch_regs(void); +void shadow_lp0_scratch_regs(void); + + extern NvRmDeviceHandle s_hRmGlobal; uintptr_t g_resume = 0, g_contextSavePA = 0, g_contextSaveVA = 0; @@ -43,6 +49,59 @@ NvU32 g_wakeupCcbp = 0, g_NumActiveCPUs, g_Sync = 0, g_ArmPerif = 0; NvU32 g_enterLP2PA = 0; NvU32 g_localTimerLoadRegister, g_localTimerCntrlRegister; NvU32 g_coreSightClock, g_currentCcbp; +volatile void *g_pPMC, *g_pAHB, *g_pCLK_RST_CONTROLLER; +volatile void *g_pEMC, *g_pMC, *g_pAPB_MISC; + +// Chip external specific wakeup events list +static const struct wakeup_source s_WakeupSources[] = +{ + WAKEUP_EXTERNAL('o', 5), //wake 0 + WAKEUP_EXTERNAL('v', 3), //wake 1 + WAKEUP_EXTERNAL('l', 1), //wake 2 + WAKEUP_EXTERNAL('b', 6), //wake 3 + WAKEUP_EXTERNAL('n', 7), //wake 4 + WAKEUP_EXTERNAL('a', 0), //wake 5 + WAKEUP_EXTERNAL('u', 5), //wake 6 + WAKEUP_EXTERNAL('u', 6), //wake 7 + WAKEUP_EXTERNAL('c', 7), //wake 8 + WAKEUP_EXTERNAL('s', 2), //wake 9 + WAKEUP_EXTERNAL( aa, 1), //wake 10 + WAKEUP_EXTERNAL('w', 3), //wake 11 + WAKEUP_EXTERNAL('w', 2), //wake 12 + WAKEUP_EXTERNAL('y', 6), //wake 13 + WAKEUP_EXTERNAL('v', 6), //wake 14 + WAKEUP_EXTERNAL('j', 7), //wake 15 + WAKEUP_INTERNAL(NvRmModuleID_Rtc, 0, 0), //wake 16 + WAKEUP_INTERNAL(NvRmModuleID_Kbc, 0, 0), //wake 17 + WAKEUP_INTERNAL(NvRmPrivModuleID_PmuExt, 0, 0), //wake 18 + //TODO: Check if USB values are correct + WAKEUP_INTERNAL(NvRmModuleID_Usb2Otg, 0, 0), //wake 19 + WAKEUP_INTERNAL(NvRmModuleID_Usb2Otg, 0, 1), //wake 20 + WAKEUP_INTERNAL(NvRmModuleID_Usb2Otg, 1, 0), //wake 21 + WAKEUP_INTERNAL(NvRmModuleID_Usb2Otg, 1, 1), //wake 22 + WAKEUP_EXTERNAL('i', 5), //wake 23 + WAKEUP_EXTERNAL('v', 2), //wake 24 + WAKEUP_EXTERNAL('s', 4), //wake 25 + WAKEUP_EXTERNAL('s', 5), //wake 26 + WAKEUP_EXTERNAL('s', 0), //wake 27 + WAKEUP_EXTERNAL('q', 6), //wake 28 + WAKEUP_EXTERNAL('q', 7), //wake 29 + WAKEUP_EXTERNAL('n', 2), //wake 30 +}; + +#define WAKEUP_SOURCE_INT_RTC 16 +#define INVALID_IRQ (0xFFFF) +#define AP20_BASE_PA_BOOT_INFO 0x40000000 +//IRQs of external wake events. +static NvIrqNumber s_WakeupIrqTable[NV_ARRAY_SIZE(s_WakeupSources)]; + +//Extended table of external wakeup events. If the wakeup source +//doesn't fall under the default 16 (chip specific) wakeup sources +//add it to this list. +static const NvIrqNumber s_WakeupIrqTableEx[] = +{ + INVALID_IRQ +}; void cpu_ap20_do_lp0(void) { @@ -70,13 +129,15 @@ void cpu_ap20_do_lp0(void) // FIXME: do we need an explicit delay? Reg = NV_REGR(s_hRmGlobal, NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0); - Reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, CPUPWRREQ_OE, DISABLE, Reg); + Reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, + CPUPWRREQ_OE, DISABLE, Reg); } - // Enter low power LP0 mode + //Enter low power LP0 mode prepare_for_wb0(); - - //TODO: Shadow required state here + shadow_lp0_scratch_regs(); + enter_power_state(POWER_STATE_LP0, 0); + shadow_runstate_scratch_regs(); if (HasPmuProperty && PmuProperty.CombinedPowerReq) { @@ -88,7 +149,7 @@ void cpu_ap20_do_lp0(void) Reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, CPUPWRREQ_OE, ENABLE, Reg); NV_REGW(s_hRmGlobal, NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0, Reg); - // FIXME: do we need an explicit delay ? + //FIXME: do we need an explicit delay ? Reg = NV_REGR(s_hRmGlobal, NvRmModuleID_Pmif, 0, APBDEV_PMC_CNTRL_0); Reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, PWRREQ_OE, DISABLE, Reg); @@ -159,6 +220,216 @@ void cpu_ap20_do_lp2(void) } } +void power_lp0_init(void) +{ + NvU32 Reg; + NvOdmPmuProperty PmuProperty; + NvBool HasPmuProperty = NvOdmQueryGetPmuProperty(&PmuProperty); + const NvOdmSocPowerStateInfo *LPStateInfo; + + LPStateInfo = NvOdmQueryLowestSocPowerState(); + + //CPU power request must be already configured and enabled in early boot + //by now. Leave it enabled to be ready for LP2/LP1. + Reg = NV_PMC_REGR(g_pPMC, CNTRL); + Reg = NV_DRF_VAL(APBDEV_PMC, CNTRL, CPUPWRREQ_OE, Reg); + if (Reg != APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_ENABLE) + goto fail; + + //If the system supports deep sleep (LP0), initialize PMC accordingly. + if (LPStateInfo->LowestPowerState == NvOdmSocPowerState_DeepSleep) + { + //Initialize the scratch registers with the current system info. + init_lp0_scratch_registers(); + + //Get the core_power_request and sys_clock_request signal polarities. + if (HasPmuProperty) + { + Reg = NV_PMC_REGR(g_pPMC, CNTRL); + + //Configure CORE power request signal polarity (the output is + //still tristated) + if (PmuProperty.CorePowerReqPolarity == NvOdmCorePowerReqPolarity_Low) + { + Reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, + PWRREQ_POLARITY, INVERT, Reg); + } + + //Enable clock request signal if supported and it's polarity. + Reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, + SYSCLK_OE, ENABLE, Reg); + if (PmuProperty.SysClockReqPolarity == NvOdmSysClockReqPolarity_Low) + { + Reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, + SYSCLK_POLARITY, INVERT, Reg); + } + + NV_PMC_REGW(g_pPMC,CNTRL,Reg); + + //Enable CORE power request output if it is connected separately + //to PMU; keep it tristated if it is combined with CPU request - + //it will be dynamically enabled/disabled on entry/exit to LP0 + if (!PmuProperty.CombinedPowerReq) + { + Reg = NV_PMC_REGR(g_pPMC, CNTRL); // make sure polarity is set + Reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, + PWRREQ_OE, ENABLE, Reg); + NV_PMC_REGW(g_pPMC,CNTRL,Reg); + } + } + + //Program the power good timer + NV_PMC_REGW(g_pPMC,PWRGOOD_TIMER,PmuProperty.PowerGoodCount); + } + + //Create the list of wakeup IRQs. + create_wakeup_irqs(); +fail: + printk("lp0 init failed!\n"); +} + +//Generate definitions of local variables to hold scratch register values. +#define SCRATCH_REG(s) static NvU32 s = 0; +SCRATCH_REGS() +#undef SCRATCH_REG + +//Generate definitions of local variables to hold shadow +//scratch register values. +#define SHADOW_REG(s) static NvU32 SHADOW_##s = 0; +SHADOW_REGS() +#undef SHADOW_REG + +static void init_lp0_scratch_registers(void) +{ + NvU32 Reg; //Module register contents + NvU32 Val; //Register field contents + + //NOTE: The SDRAM registers have already been saved + //by the bootloader + + //Generate reads to the shadowed PMC scratch registers to copy the current + //values while we populate the register with their LP0 values. + #define SHADOW_REG(s) SHADOW_##s = NV_PMC_REGR(g_pPMC, s); + SHADOW_REGS() + #undef SHADOW_REG + + //Define the transformation macro that will read and pull apart the + // module register values and pack them into PMC scratch regsiters. + + //REG(s,d,r,f) + //s = destination Scratch register + //d = Device name + //r = Register name + //f = register Field + #define REG(s,d,r,f) \ + Reg = NV_DR_REGR(d,r); \ + Val = NV_DRF_VAL(d,r,f,Reg); \ + s = NV_FLD_SET_SDRF_NUM(s,d,r,f,Val); + + //Instantiate all of the register transformations. + REGS() + #undef REG + #undef RAM + #undef CONSTANT + + //Generate writes to the PMC scratch registers to copy the local + //variables to the actual registers. + #define SCRATCH_REG(s) NV_PMC_REGW(g_pPMC, s, s); + SCRATCH_REGS() + #undef SCRATCH_REG + + //Generate writes to the shadowed PMC scratch registers to restore the + //"normal" values expected by RM. + #define SHADOW_REG(s) NV_PMC_REGW(g_pPMC, s, SHADOW_##s); + SHADOW_REGS() + #undef SHADOW_REG + + return; +} + +void shadow_runstate_scratch_regs(void) +{ + //Generate writes to the shadowed PMC scratch registers to restore the + //"normal" running mode values expected by RM. + #define SHADOW_REG(s) NV_PMC_REGW(g_pPMC, s, SHADOW_##s); + SHADOW_REGS() + #undef SHADOW_REG +} + +void shadow_lp0_scratch_regs(void) +{ + //Generate reads of the shadowed PMC scratch registers to copy the current + //values while we populate the register with their LP0 values. + #define SHADOW_REG(s) SHADOW_##s = NV_PMC_REGR(g_pPMC, s); + SHADOW_REGS() + #undef SHADOW_REG + + // Generate writes to the shadowed PMC scratch registers + //for the LP0 values. + #define SHADOW_REG(s) NV_PMC_REGW(g_pPMC, s, s); + SHADOW_REGS() + #undef SHADOW_REG +} + +static void create_wakeup_irqs(void) +{ + NvU32 WakeupTableSize; + NvU32 Count; + NvU32 PadNumber; + const NvOdmWakeupPadInfo* pNvOdmWakeupPadInfo; + const NvOdmWakeupPadInfo* pWakeupPad; + + //Initialize the wakeup irq table. + for (Count = 0; Count < NV_ARRAY_SIZE(s_WakeupIrqTable); Count++) + { + s_WakeupIrqTable[Count] = INVALID_IRQ; + } + + //Get the wakeup sources table from odm. + pNvOdmWakeupPadInfo = NvOdmQueryGetWakeupPadTable(&WakeupTableSize); + if (WakeupTableSize > NV_ARRAY_SIZE(s_WakeupSources)) + goto fail; + + //If there is a wakeup pad information table + if (pNvOdmWakeupPadInfo) + { + //Then for each pad ... + for (Count = 0; Count < WakeupTableSize; Count++) + { + //... get it's pad number. + pWakeupPad = &pNvOdmWakeupPadInfo[Count]; + PadNumber = pWakeupPad->WakeupPadNumber; + + if (PadNumber >= NV_ARRAY_SIZE(s_WakeupSources)) + goto fail; + + //If the pad is enabled as a wakeup source... + if (pWakeupPad->enable) + { + //... get it's IRQ number. + s_WakeupIrqTable[PadNumber] = NvRmGetIrqForLogicalInterrupt( + s_hRmGlobal, + s_WakeupSources[PadNumber].Module, + s_WakeupSources[PadNumber].Index); + if (s_WakeupIrqTable[PadNumber] == INVALID_IRQ) + goto fail; + } + } + } + + // Create internal events those are transparent to ODM. + //These events will always be enabled. + s_WakeupIrqTable[WAKEUP_SOURCE_INT_RTC] = + NvRmGetIrqForLogicalInterrupt(s_hRmGlobal, + s_WakeupSources[WAKEUP_SOURCE_INT_RTC].Module, + s_WakeupSources[WAKEUP_SOURCE_INT_RTC].Index); + + return; +fail: + printk("Failed to create wakeup irqs\n"); + return; +} + static NvU32 select_wakeup_pll(void) { NvU32 Reg = 0; // Scratch register diff --git a/arch/arm/mach-tegra/power.h b/arch/arm/mach-tegra/power.h index f55556a150b0..53e9e9568fd2 100644 --- a/arch/arm/mach-tegra/power.h +++ b/arch/arm/mach-tegra/power.h @@ -31,6 +31,8 @@ #include "ap20/arapbdma.h" #include "ap20/arapbdmachan.h" #include "ap20/armc.h" +#include "ap20/arahb_arbc.h" +#include "ap20/aremc.h" #include "ap15/arictlr.h" #include "ap15/argpio.h" #include "nvrm_hardware_access.h" @@ -87,12 +89,371 @@ extern NvRmDeviceHandle s_hRmGlobal; #define NV_MC_REGW(pBase, reg, val)\ NV_WRITE32( (((NvUPtr)(pBase)) + MC_##reg##_0), (val)) +#define NV_PMC_REGR(pBase, reg)\ + NV_READ32( (((NvUPtr)(pBase)) + APBDEV_PMC_##reg##_0)) +#define NV_PMC_REGW(pBase, reg, val)\ + NV_WRITE32( (((NvUPtr)(pBase)) + APBDEV_PMC_##reg##_0), (val)) + #define CAR_CLK_SOURCES_OFFSET_START CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0 #define CAR_CLK_SOURCES_OFFSET_END CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0 #define CAR_CLK_SOURCES_REGISTER_COUNT\ ((CAR_CLK_SOURCES_OFFSET_END - CAR_CLK_SOURCES_OFFSET_START +\ sizeof(NvU32)) / sizeof(NvU32)) +#define NV_DR_REGR(d,r)\ + NV_READ32( ((NvUPtr)(g_p##d)) + d##_##r##_0) + + +//------------------------------------------------------------------------------ +// Boot ROM PMC scratch map name remapping to fix broken names (see bug 542815). +//------------------------------------------------------------------------------ + +//Correct name \ Broken name from nvboot_pmc_scratch_map.h +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_RANGE\ + APBDEV_PMC_SCRATCH2_0_CLK_RST_OSC_CTRL_XOBP_RANGE +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_RANGE\ + APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVM_RANGE +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_RANGE\ + APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVN_RANGE +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_RANGE\ + APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVP_RANGE +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_RANGE\ + APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_CPCON_RANGE +#define APBDEV_PMC_SCRATCH2_0_CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_RANGE\ + APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_LFCON_RANGE +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_RANGE\ + APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVP_RANGE +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_RANGE\ + APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVN_RANGE +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_RANGE\ + APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVM_RANGE +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_RANGE\ + APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_CPCON_RANGE +#define APBDEV_PMC_SCRATCH3_0_CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_RANGE\ + APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_LFCON_RANGE + +/** NV_SDRF_NUM - define a new scratch register value. + @param s scratch register name (APBDEV_PMC_s) + @param d register domain (hardware block) + @param r register name + @param f register field + @param n defined value for the field + */ +#define NV_SDRF_NUM(s,d,r,f,n) \ + (((n)& NV_FIELD_MASK(APBDEV_PMC_##s##_0_##d##_##r##_0_##f##_RANGE)) << \ + NV_FIELD_SHIFT(APBDEV_PMC_##s##_0_##d##_##r##_0_##f##_RANGE)) + +/** NV_FLD_SET_SDRF_NUM - modify a scratch register field. + @param s scratch register name (APBDEV_PMC_s) + @param d register domain (hardware block) + @param r register name + @param f register field + @param n numeric field value + */ +#define NV_FLD_SET_SDRF_NUM(s,d,r,f,n) \ + ((s & ~NV_FIELD_SHIFTMASK(APBDEV_PMC_##s##_0_##d##_##r##_0_##f##_RANGE)) |\ + NV_SDRF_NUM(s,d,r,f,n)) + + +/** SHADOW_REGS() - Shadowed PMC scratch registers that must be saved/restored + across low power transitions because they are used by RM + for other purposes. + SHADOW_REG(s) - Shadowed PMC scratch register name: + @param s Scratch register name (APBDEV_PMC_s) + */ +#define SHADOW_REGS()\ + SHADOW_REG(SCRATCH20) \ + SHADOW_REG(SCRATCH21) \ + /* End-of-List*/ + + +/** SCRATCH_REGS() - PMC scratch registers (list of SCRATCH_REG() macros). + SCRATCH_REG(s) - PMC scratch register name: + + @param s Scratch register name (APBDEV_PMC_s) + */ +#define SCRATCH_REGS() \ + SCRATCH_REG(SCRATCH2) \ + SCRATCH_REG(SCRATCH3) \ + SCRATCH_REG(SCRATCH4) \ + SCRATCH_REG(SCRATCH5) \ + SCRATCH_REG(SCRATCH6) \ + SCRATCH_REG(SCRATCH7) \ + SCRATCH_REG(SCRATCH8) \ + SCRATCH_REG(SCRATCH9) \ + SCRATCH_REG(SCRATCH10) \ + SCRATCH_REG(SCRATCH11) \ + SCRATCH_REG(SCRATCH12) \ + SCRATCH_REG(SCRATCH13) \ + SCRATCH_REG(SCRATCH14) \ + SCRATCH_REG(SCRATCH15) \ + SCRATCH_REG(SCRATCH16) \ + SCRATCH_REG(SCRATCH17) \ + SCRATCH_REG(SCRATCH18) \ + SCRATCH_REG(SCRATCH19) \ + SCRATCH_REG(SCRATCH20) \ + SCRATCH_REG(SCRATCH21) \ + SCRATCH_REG(SCRATCH22) \ + SCRATCH_REG(SCRATCH23) \ + SCRATCH_REG(SCRATCH24) \ + SCRATCH_REG(SCRATCH25) \ + SCRATCH_REG(SCRATCH35) \ + SCRATCH_REG(SCRATCH36) \ + SCRATCH_REG(SCRATCH40) \ + /* End-of-List*/ + +/** REGS() - Scratch mapping registers (list of REG() macros). + REG(s,d,r,f) - Scratch mapping register entry: + + @param s scratch register name (APBDEV_PMC_s) + @param d register domain (hardware block) + @param r register name + @param f register field + */ +#define REGS() \ + /* AHB Group */ \ + REG(SCRATCH25, AHB, ARBITRATION_XBAR_CTRL, POST_DIS) \ + REG(SCRATCH25, AHB, ARBITRATION_XBAR_CTRL, HOLD_DIS) \ + REG(SCRATCH25, AHB, ARBITRATION_XBAR_CTRL, MEM_INIT_DONE) \ + /* CLK_RST Group */ \ + REG(SCRATCH2, CLK_RST_CONTROLLER, OSC_CTRL, XOBP) \ + REG(SCRATCH2, CLK_RST_CONTROLLER, PLLM_BASE, PLLM_DIVM) \ + REG(SCRATCH2, CLK_RST_CONTROLLER, PLLM_BASE, PLLM_DIVN) \ + REG(SCRATCH2, CLK_RST_CONTROLLER, PLLM_BASE, PLLM_DIVP) \ + REG(SCRATCH2, CLK_RST_CONTROLLER, PLLM_MISC, PLLM_CPCON) \ + REG(SCRATCH2, CLK_RST_CONTROLLER, PLLM_MISC, PLLM_LFCON) \ + /**/ \ + REG(SCRATCH3, CLK_RST_CONTROLLER, PLLX_BASE, PLLX_DIVP) \ + REG(SCRATCH3, CLK_RST_CONTROLLER, PLLX_BASE, PLLX_DIVN) \ + REG(SCRATCH3, CLK_RST_CONTROLLER, PLLX_BASE, PLLX_DIVM) \ + REG(SCRATCH3, CLK_RST_CONTROLLER, PLLX_MISC, PLLX_CPCON) \ + REG(SCRATCH3, CLK_RST_CONTROLLER, PLLX_MISC, PLLX_LFCON) \ + /* EMC Group */ \ + REG(SCRATCH4, EMC, FBIO_SPARE, CFG_FBIO_SPARE_WB0) \ + /**/ \ + REG(SCRATCH5, EMC, R2W, R2W) \ + REG(SCRATCH5, EMC, RAS, RAS) \ + REG(SCRATCH5, EMC, RC, RC) \ + REG(SCRATCH5, EMC, RFC, RFC) \ + REG(SCRATCH5, EMC, RP, RP) \ + /**/ \ + REG(SCRATCH6, EMC, R2P, R2P) \ + REG(SCRATCH6, EMC, RD_RCD, RD_RCD) \ + REG(SCRATCH6, EMC, RRD, RRD) \ + REG(SCRATCH6, EMC, W2P, W2P) \ + REG(SCRATCH6, EMC, W2R, W2R) \ + REG(SCRATCH6, EMC, WR_RCD, WR_RCD) \ + /**/ \ + REG(SCRATCH7, EMC, CFG_2, CLKCHANGE_SR_ENABLE) \ + REG(SCRATCH7, EMC, CFG_2, USE_ADDR_CLK) \ + REG(SCRATCH7, EMC, PCHG2PDEN, PCHG2PDEN) \ + REG(SCRATCH7, EMC, QRST, QRST) \ + REG(SCRATCH7, EMC, QSAFE, QSAFE) \ + REG(SCRATCH7, EMC, QUSE, QUSE) \ + REG(SCRATCH7, EMC, RDV, RDV) \ + REG(SCRATCH7, EMC, REXT, REXT) \ + REG(SCRATCH7, EMC, WDV, WDV) \ + /**/ \ + REG(SCRATCH8, EMC, BURST_REFRESH_NUM, BURST_REFRESH_NUM) \ + REG(SCRATCH8, EMC, PDEX2RD, PDEX2RD) \ + REG(SCRATCH8, EMC, PDEX2WR, PDEX2WR) \ + REG(SCRATCH8, EMC, REFRESH, REFRESH_LO) \ + REG(SCRATCH8, EMC, REFRESH, REFRESH) \ + REG(SCRATCH8, EMC, TCLKSTABLE, TCLKSTABLE) \ + /**/ \ + REG(SCRATCH9, EMC, ACT2PDEN, ACT2PDEN) \ + REG(SCRATCH9, EMC, AR2PDEN, AR2PDEN) \ + REG(SCRATCH9, EMC, RW2PDEN, RW2PDEN) \ + REG(SCRATCH9, EMC, TCKE, TCKE) \ + REG(SCRATCH9, EMC, TXSR, TXSR) \ + /**/ \ + REG(SCRATCH10, EMC, DBG, AP_REQ_BUSY_CTRL) \ + REG(SCRATCH10, EMC, DBG, CFG_PRIORITY) \ + REG(SCRATCH10, EMC, DBG, FORCE_UPDATE) \ + REG(SCRATCH10, EMC, DBG, MRS_WAIT) \ + REG(SCRATCH10, EMC, DBG, PERIODIC_QRST) \ + REG(SCRATCH10, EMC, DBG, READ_DQM_CTRL) \ + REG(SCRATCH10, EMC, DBG, READ_MUX) \ + REG(SCRATCH10, EMC, DBG, WRITE_MUX) \ + REG(SCRATCH10, EMC, TCLKSTOP, TCLKSTOP) \ + REG(SCRATCH10, EMC, TREFBW, TREFBW) \ + REG(SCRATCH10, EMC, TRPAB, TRPAB) \ + /**/ \ + REG(SCRATCH11, EMC, FBIO_DQSIB_DLY_MSB, CFG_DQSIB_DLY_MSB_BYTE_0) \ + REG(SCRATCH11, EMC, FBIO_DQSIB_DLY_MSB, CFG_DQSIB_DLY_MSB_BYTE_1) \ + REG(SCRATCH11, EMC, FBIO_DQSIB_DLY_MSB, CFG_DQSIB_DLY_MSB_BYTE_2) \ + REG(SCRATCH11, EMC, FBIO_DQSIB_DLY_MSB, CFG_DQSIB_DLY_MSB_BYTE_3) \ + REG(SCRATCH11, EMC, FBIO_QUSE_DLY_MSB, CFG_QUSE_DLY_MSB_BYTE_0) \ + REG(SCRATCH11, EMC, FBIO_QUSE_DLY_MSB, CFG_QUSE_DLY_MSB_BYTE_1) \ + REG(SCRATCH11, EMC, FBIO_QUSE_DLY_MSB, CFG_QUSE_DLY_MSB_BYTE_2) \ + REG(SCRATCH11, EMC, FBIO_QUSE_DLY_MSB, CFG_QUSE_DLY_MSB_BYTE_3) \ + REG(SCRATCH11, EMC, QUSE_EXTRA, QUSE_EXTRA) \ + REG(SCRATCH11, EMC, TFAW, TFAW) \ + /**/ \ + REG(SCRATCH12, EMC, FBIO_DQSIB_DLY, CFG_DQSIB_DLY_BYTE_0) \ + REG(SCRATCH12, EMC, FBIO_DQSIB_DLY, CFG_DQSIB_DLY_BYTE_1) \ + REG(SCRATCH12, EMC, FBIO_DQSIB_DLY, CFG_DQSIB_DLY_BYTE_2) \ + REG(SCRATCH12, EMC, FBIO_DQSIB_DLY, CFG_DQSIB_DLY_BYTE_3) \ + /**/ \ + REG(SCRATCH13, EMC, FBIO_QUSE_DLY, CFG_QUSE_DLY_BYTE_0) \ + REG(SCRATCH13, EMC, FBIO_QUSE_DLY, CFG_QUSE_DLY_BYTE_1) \ + REG(SCRATCH13, EMC, FBIO_QUSE_DLY, CFG_QUSE_DLY_BYTE_2) \ + REG(SCRATCH13, EMC, FBIO_QUSE_DLY, CFG_QUSE_DLY_BYTE_3) \ + /**/ \ + REG(SCRATCH14, EMC, CFG_CLKTRIM_0, CFG_DATA0_CLKTRIM) \ + REG(SCRATCH14, EMC, CFG_CLKTRIM_0, CFG_DATA1_CLKTRIM) \ + REG(SCRATCH14, EMC, CFG_CLKTRIM_0, CFG_DATA2_CLKTRIM) \ + REG(SCRATCH14, EMC, CFG_CLKTRIM_0, CFG_DATA3_CLKTRIM) \ + REG(SCRATCH14, EMC, CFG_CLKTRIM_0, CFG_MCLK_ADDR_CLKTRIM) \ + /**/ \ + REG(SCRATCH15, EMC, AUTO_CAL_CONFIG, AUTO_CAL_ENABLE) \ + REG(SCRATCH15, EMC, AUTO_CAL_CONFIG, AUTO_CAL_OVERRIDE) \ + REG(SCRATCH15, EMC, AUTO_CAL_CONFIG, AUTO_CAL_PD_OFFSET) \ + REG(SCRATCH15, EMC, AUTO_CAL_CONFIG, AUTO_CAL_PU_OFFSET) \ + REG(SCRATCH15, EMC, AUTO_CAL_CONFIG, AUTO_CAL_STEP) \ + REG(SCRATCH15, EMC, FBIO_CFG1, CFG_DEN_EARLY) \ + REG(SCRATCH15, EMC, FBIO_CFG5, CTT_TERMINATION) \ + REG(SCRATCH15, EMC, FBIO_CFG5, DIFFERENTIAL_DQS) \ + REG(SCRATCH15, EMC, FBIO_CFG5, DQS_PULLD) \ + REG(SCRATCH15, EMC, FBIO_CFG5, DRAM_TYPE) \ + REG(SCRATCH15, EMC, FBIO_CFG5, DRAM_WIDTH) \ + REG(SCRATCH15, EMC, FBIO_CFG6, CFG_QUSE_LATE) \ + /**/ \ + REG(SCRATCH16, EMC, AUTO_CAL_INTERVAL, AUTO_CAL_INTERVAL) \ + REG(SCRATCH16, EMC, CFG_2, CLKCHANGE_PD_ENABLE) \ + REG(SCRATCH16, EMC, CFG_2, CLKCHANGE_REQ_ENABLE) \ + REG(SCRATCH16, EMC, CFG_2, PIN_CONFIG) \ + /**/ \ + REG(SCRATCH17, EMC, ADR_CFG, EMEM_BANKWIDTH) \ + REG(SCRATCH17, EMC, ADR_CFG, EMEM_COLWIDTH) \ + REG(SCRATCH17, EMC, ADR_CFG, EMEM_DEVSIZE) \ + REG(SCRATCH17, EMC, ADR_CFG, EMEM_NUMDEV) \ + REG(SCRATCH17, EMC, CFG, AUTO_PRE_RD) \ + REG(SCRATCH17, EMC, CFG, AUTO_PRE_WR) \ + REG(SCRATCH17, EMC, CFG, CLEAR_AP_PREV_SPREQ) \ + REG(SCRATCH17, EMC, CFG, DRAM_ACPD) \ + REG(SCRATCH17, EMC, CFG, DRAM_CLKSTOP_PDSR_ONLY) \ + REG(SCRATCH17, EMC, CFG, DRAM_CLKSTOP) \ + REG(SCRATCH17, EMC, CFG, PRE_IDLE_CYCLES) \ + REG(SCRATCH17, EMC, CFG, PRE_IDLE_EN) \ + REG(SCRATCH17, EMC, CFG_DIG_DLL, CFG_DLL_LOCK_LIMIT) \ + REG(SCRATCH17, EMC, CFG_DIG_DLL, CFG_DLL_MODE) \ + /**/ \ + REG(SCRATCH18, EMC, ADR_CFG_1, EMEM1_BANKWIDTH) \ + REG(SCRATCH18, EMC, ADR_CFG_1, EMEM1_COLWIDTH) \ + REG(SCRATCH18, EMC, ADR_CFG_1, EMEM1_DEVSIZE) \ + REG(SCRATCH18, EMC, CTT_TERM_CTRL, TERM_DRVUP) \ + /**/ \ + REG(SCRATCH19, EMC, CFG_DIG_DLL, CFG_DLI_TRIMMER_EN) \ + REG(SCRATCH19, EMC, CFG_DIG_DLL, CFG_DLL_EN) \ + REG(SCRATCH19, EMC, CFG_DIG_DLL, CFG_DLL_LOWSPEED) \ + REG(SCRATCH19, EMC, CFG_DIG_DLL, CFG_DLL_OVERRIDE_EN) \ + REG(SCRATCH19, EMC, CFG_DIG_DLL, CFG_DLL_UDSET) \ + REG(SCRATCH19, EMC, CFG_DIG_DLL, CFG_PERBYTE_TRIMMER_OVERRIDE) \ + REG(SCRATCH19, EMC, CFG_DIG_DLL, CFG_USE_SINGLE_DLL) \ + /**/ \ + REG(SCRATCH20, EMC, CFG_CLKTRIM_1, CFG_DQS0_CLKTRIM) \ + REG(SCRATCH20, EMC, CFG_CLKTRIM_1, CFG_DQS1_CLKTRIM) \ + REG(SCRATCH20, EMC, CFG_CLKTRIM_1, CFG_DQS2_CLKTRIM) \ + REG(SCRATCH20, EMC, CFG_CLKTRIM_1, CFG_DQS3_CLKTRIM) \ + REG(SCRATCH20, EMC, CFG_CLKTRIM_1, CFG_MCLK_CLKTRIM) \ + /**/ \ + REG(SCRATCH21, EMC, CFG_CLKTRIM_2, CFG_CMD_CLKTRIM) \ + REG(SCRATCH21, EMC, CFG_CLKTRIM_2, CFG_DQ0_CLKTRIM) \ + REG(SCRATCH21, EMC, CFG_CLKTRIM_2, CFG_DQ1_CLKTRIM) \ + REG(SCRATCH21, EMC, CFG_CLKTRIM_2, CFG_DQ2_CLKTRIM) \ + REG(SCRATCH21, EMC, CFG_CLKTRIM_2, CFG_DQ3_CLKTRIM) \ + /**/ \ + REG(SCRATCH22, EMC, CFG_DIG_DLL, CFG_DLL_OVERRIDE_VAL) \ + REG(SCRATCH22, EMC, DLL_XFORM_DQS, XFORM_DQS_MULT) \ + REG(SCRATCH22, EMC, DLL_XFORM_DQS, XFORM_DQS_OFFS) \ + /**/ \ + REG(SCRATCH23, EMC, DLL_XFORM_QUSE, XFORM_QUSE_MULT) \ + REG(SCRATCH23, EMC, DLL_XFORM_QUSE, XFORM_QUSE_OFFS) \ + REG(SCRATCH23, EMC, ODT_READ, DISABLE_ODT_DURING_READ) \ + REG(SCRATCH23, EMC, ODT_READ, ODT_B4_READ) \ + REG(SCRATCH23, EMC, ODT_READ, ODT_RD_DELAY) \ + REG(SCRATCH23, EMC, ODT_WRITE, ENABLE_ODT_DURING_WRITE) \ + REG(SCRATCH23, EMC, ODT_WRITE, ODT_B4_WRITE) \ + REG(SCRATCH23, EMC, ODT_WRITE, ODT_WR_DELAY) \ + /**/ \ + REG(SCRATCH35, EMC, ZCAL_REF_CNT, ZCAL_REF_INTERVAL) \ + REG(SCRATCH35, EMC, ZCAL_WAIT_CNT, ZCAL_WAIT_CNT) \ + REG(SCRATCH36, EMC, CTT_TERM_CTRL, TERM_DRVDN) \ + REG(SCRATCH36, EMC, CTT_TERM_CTRL, TERM_OFFSET) \ + REG(SCRATCH36, EMC, CTT_TERM_CTRL, TERM_OVERRIDE) \ + REG(SCRATCH36, EMC, CTT_TERM_CTRL, TERM_SLOPE) \ + REG(SCRATCH36, EMC, ZCAL_MRW_CMD, ZQ_MRW_MA) \ + REG(SCRATCH36, EMC, ZCAL_MRW_CMD, ZQ_MRW_OP) \ + /* MC Group */ \ + REG(SCRATCH17, MC, LOWLATENCY_CONFIG, MPCORER_LL_CTRL) \ + REG(SCRATCH17, MC, LOWLATENCY_CONFIG, MPCORER_LL_SEND_BOTH) \ + /**/ \ + REG(SCRATCH19, MC, EMEM_CFG, EMEM_SIZE_KB) \ + /**/ \ + REG(SCRATCH22, MC, LOWLATENCY_CONFIG, LL_DRAM_INTERLEAVE) \ + /* APB_MISC Group */ \ + REG(SCRATCH2, APB_MISC, GP_XM2CFGAPADCTRL, CFG2TMC_XM2CFGA_PREEMP_EN) \ + REG(SCRATCH2, APB_MISC, GP_XM2CFGDPADCTRL, CFG2TMC_XM2CFGD_SCHMT_EN) \ + /**/ \ + REG(SCRATCH3, APB_MISC, GP_XM2CFGCPADCTRL2, CFG2TMC_XM2CFGC_VREF_DQ) \ + REG(SCRATCH3, APB_MISC, GP_XM2CFGCPADCTRL, CFG2TMC_XM2CFGC_SCHMT_EN) \ + REG(SCRATCH3, APB_MISC, GP_XM2CLKCFGPADCTRL, CFG2TMC_XM2CLKCFG_PREEMP_EN) \ + /**/ \ + REG(SCRATCH11, APB_MISC, GP_XM2CFGCPADCTRL2, CFG2TMC_XM2CFGC_VREF_DQ_EN) \ + REG(SCRATCH11, APB_MISC, GP_XM2CFGCPADCTRL2, CFG2TMC_XM2CFGC_VREF_DQS) \ + /**/ \ + REG(SCRATCH18, APB_MISC, GP_XM2COMPPADCTRL, CFG2TMC_XM2COMP_VREF_SEL) \ + REG(SCRATCH18, APB_MISC, GP_XM2VTTGENPADCTRL, CFG2TMC_XM2VTTGEN_CAL_DRVDN) \ + REG(SCRATCH18, APB_MISC, GP_XM2VTTGENPADCTRL, CFG2TMC_XM2VTTGEN_CAL_DRVUP) \ + REG(SCRATCH18, APB_MISC, GP_XM2VTTGENPADCTRL, CFG2TMC_XM2VTTGEN_SHORT_PWRGND) \ + REG(SCRATCH18, APB_MISC, GP_XM2VTTGENPADCTRL, CFG2TMC_XM2VTTGEN_SHORT) \ + REG(SCRATCH18, APB_MISC, GP_XM2VTTGENPADCTRL, CFG2TMC_XM2VTTGEN_VAUXP_LEVEL) \ + REG(SCRATCH18, APB_MISC, GP_XM2VTTGENPADCTRL, CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL) \ + /**/ \ + REG(SCRATCH20, APB_MISC, GP_XM2CFGCPADCTRL2, CFG2TMC_XM2CFGC_CTT_HIZ_EN) \ + REG(SCRATCH20, APB_MISC, GP_XM2CFGCPADCTRL2, CFG2TMC_XM2CFGC_VREF_DQS_EN) \ + /**/ \ + REG(SCRATCH21, APB_MISC, GP_XM2CFGCPADCTRL2, CFG2TMC_XM2CFGC_PREEMP_EN) \ + REG(SCRATCH21, APB_MISC, GP_XM2CFGCPADCTRL2, CFG2TMC_XM2CFGC_RX_FT_REC_EN) \ + /**/ \ + REG(SCRATCH40, APB_MISC, GP_XM2CFGDPADCTRL2, CFG2TMC_XM2CFGD0_DLYIN_TRM) \ + REG(SCRATCH40, APB_MISC, GP_XM2CFGDPADCTRL2, CFG2TMC_XM2CFGD1_DLYIN_TRM) \ + REG(SCRATCH40, APB_MISC, GP_XM2CFGDPADCTRL2, CFG2TMC_XM2CFGD2_DLYIN_TRM) \ + REG(SCRATCH40, APB_MISC, GP_XM2CFGDPADCTRL2, CFG2TMC_XM2CFGD3_DLYIN_TRM) \ + REG(SCRATCH40, APB_MISC, GP_XM2CFGDPADCTRL2, CFG2TMC_XM2CFGD_CTT_HIZ_EN) \ + REG(SCRATCH40, APB_MISC, GP_XM2CFGDPADCTRL2, CFG2TMC_XM2CFGD_PREEMP_EN) \ + REG(SCRATCH40, APB_MISC, GP_XM2CFGDPADCTRL2, CFG2TMC_XM2CFGD_RX_FT_REC_EN) \ + /* End-of-List */ + +#define GPIO_PORT(x) ((x) - 'a') +#define GPIO_PORTS_PER_INSTANCE (4) +#define GPIO_BITS_PER_PORT (8) + +#define aa ('z'+1) // GPIO port AA +#define ab ('z'+2) // GPIO port AB + +//------------------------------------------------------------------------------ +// Wakeup source table macros +//------------------------------------------------------------------------------ + +/** WAKEUP_INTERNAL(m,i,x) - Internal wakeup module interrupt sources + + @param m Module id + @param i Module instance + @param x Module interrupt index + */ +#define WAKEUP_INTERNAL(m,i,x) { NVRM_MODULE_ID((m), (i)), (x) } + +/** WAKEUP_EXTERNAL(p, b) - External wakeup module interrupt sources + + @param p GPIO port (e.g., 'a', 'b', etc.) + @param b GPIO port bit + */ +#define WAKEUP_EXTERNAL(p,b)\ + {NVRM_MODULE_ID(NvRmPrivModuleID_Gpio,GPIO_PORT(p)/GPIO_PORTS_PER_INSTANCE),\ + (((GPIO_PORT(p) % GPIO_PORTS_PER_INSTANCE)*GPIO_BITS_PER_PORT) + (b)) } + typedef struct { NvU32 *pBase; @@ -113,6 +474,12 @@ struct power_context power_module_context mc; }; +struct wakeup_source +{ + NvU32 Module; + NvU32 Index; +}; + typedef enum { PowerModuleContext_Init, @@ -139,3 +506,5 @@ typedef enum POWER_STATE_LP1, POWER_STATE_LP0, } PowerState; + +typedef NvU16 NvIrqNumber; |