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authorAlex Frid <afrid@nvidia.com>2011-05-11 19:22:43 -0700
committerVarun Colbert <vcolbert@nvidia.com>2011-05-17 11:53:22 -0700
commitdda707a20776c053918b39e6e235338c16bc73bb (patch)
tree50f4708dcc4b725cd18f7139aa61906f9a0e0a5c /arch
parentaec1359a24a0ae8a381c48217fd710d05c0c6fbd (diff)
ARM: tegra: power: Update Tegra3 CPU DVFS table
Change-Id: I3164bb2d86619b891a647b5e6550470c509eb403 Reviewed-on: http://git-master/r/31308 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/tegra3_dvfs.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
index e89b3e01a9c0..804a40c68e02 100644
--- a/arch/arm/mach-tegra/tegra3_dvfs.c
+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
@@ -113,8 +113,11 @@ static struct dvfs_relationship tegra3_dvfs_relationships[] = {
}
static struct dvfs cpu_dvfs_table[] = {
- /* Cpu voltages (mV): 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125 */
- CPU_DVFS("cpu_g", 0, 0, MHZ, 1, 1, 614, 614, 714, 714, 815, 815, 915, 915, 1000),
+ /* Cpu voltages (mV): 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125 */
+ CPU_DVFS("cpu_g", 0, 0, MHZ, 399, 399, 541, 541, 684, 684, 817, 817, 817, 1026, 1102, 1149, 1187, 1225, 1282, 1300),
+ CPU_DVFS("cpu_g", 0, 1, MHZ, 481, 481, 652, 652, 807, 807, 948, 948, 948, 1117, 1171, 1206, 1300),
+ CPU_DVFS("cpu_g", 0, 2, MHZ, 540, 540, 711, 711, 883, 883, 1039, 1039, 1039, 1178, 1206, 1300),
+ CPU_DVFS("cpu_g", 0, 3, MHZ, 570, 570, 777, 777, 931, 931, 1102, 1102, 1102, 1216, 1300),
/*
* "Safe entry" to be used when no match for chip speedo, process